Method and structure of forming controllable unmerged epitaxial material
A method of forming a semiconductor device that includes forming a plurality of semiconductor pillars. A dielectric spacer is formed between at least one set of adjacent semiconductor pillars. Semiconductor material is epitaxially formed on sidewalls of the adjacent semiconductor pillars, wherein the dielectric spacer obstructs a first portion of epitaxial semiconductor material formed on a first semiconductor pillar from merging with a second portion of epitaxial semiconductor material formed on a second semiconductor pillar.
1. A semiconductor device comprising:
a plurality of fin structures;
a dielectric spacer in a space between adjacent fin structures of said plurality of fin structures; and
an epitaxial semiconductor present on a first sidewall of a first fin structure of the adjacent fin structures and a second sidewall of a second fin structure of the adjacent fins structures, wherein the epitaxial semiconductor material that is in contact with the first and second fin structures also contacts the dielectric spacer.
2. The semiconductor device of claim 1 , wherein the epitaxial semiconductor present on the first fin structure is separate from the epitaxial semiconductor present on the second fin structure.
3. The semiconductor device of claim 1 wherein the epitaxial semiconductor material is present on source and drain region portions of the plurality of fin structures, and a gate structure is present on a channel region portion of the plurality of fin structures between the source and drain region portions.
4. The semiconductor device of claim 3 , wherein the gate structure comprises a gate dielectric on the channel region portion and at least one gate conductor on the gate dielectric.
5. The semiconductor device of claim 1 , wherein the dielectric spacer has a height that is less than a height of the plurality of fin structures.
6. The semiconductor device of claim 1 , wherein the plurality of fin structures includes a first group of fin structures having a first pitch and a second group of fin structures having a second pitch.
7. The semiconductor device of claim 6 , wherein the dielectric spacer is self-aligned to a central position of the first pitch and second pitch.
8. The semiconductor device of claim 7 , wherein the first pitch is greater than the second pitch, and the dielectric spacer between adjacent semiconductor fin structures in the first group having the first pitch has a width that is greater than the dielectric spacer between adjacent semiconductor fin structures in the second group having the second pitch.
9. A semiconductor device comprising:
a first group of fin structures having a first pitch and a second group of fin structures having a second pitch on a same substrate, wherein the first pitch is greater than the second pitch;
a dielectric spacer in a space between adjacent fin structures that is self-aligned to a central position of the first pitch and second pitch, the dielectric spacer between adjacent semiconductor fin structures in the first group having the first pitch has a width that is greater than the dielectric spacer between adjacent semiconductor fin structures in the second group having the second pitch; and
an epitaxial semiconductor present on a first sidewall of a first fin structure of the adjacent fin structures and a second sidewall of a second fin structure of the adjacent fins structures in the first and second group of fin structures, wherein the epitaxial semiconductor material that is in contact with the first and second fin structures also contacts the dielectric spacer.
10. The semiconductor device of claim 9 , wherein the epitaxial semiconductor present on the first fin structure is separate from the epitaxial semiconductor present on the second fin structure.
11. The semiconductor device of claim 9 wherein the epitaxial semiconductor material is present on source and drain region portions of the plurality of fin structures, and a gate structure is present on a channel region portion of the plurality of fin structures between the source and drain region portions.
12. The semiconductor device of claim 11 , wherein the gate structure comprises a gate dielectric on the channel region portion and at least one gate conductor on the gate dielectric.
13. The semiconductor device of claim 9 , wherein the dielectric spacer has a height that is less than a height of the plurality of fin structures.
14. A semiconductor device comprising:
a plurality of fin structures;
a dielectric spacer in a space between adjacent fin structures of said plurality of fin structures, wherein the dielectric spacer has a height that is less than a height of the plurality of fin structures; and
an epitaxial semiconductor present on a first sidewall of a first fin structure of the adjacent fin structures and a second sidewall of a second fin structure of the adjacent fins structures, wherein the epitaxial semiconductor material that is in contact with the first and second fin structures also contacts the dielectric spacer.
15. The semiconductor device of claim 14 , wherein the epitaxial semiconductor present on the first fin structure is separate from the epitaxial semiconductor present on the second fin structure.
16. The semiconductor device of claim 14 , wherein the epitaxial semiconductor material is present on source and drain region portions of the plurality of fin structures, and a gate structure is present on a channel region portion of the plurality of fin structures between the source and drain region portions.
17. The semiconductor device of claim 14 , wherein the gate structure comprises a gate dielectric on the channel region portion and at least one gate conductor on the gate dielectric.
18. The semiconductor device of claim 14 , wherein the plurality of fin structures includes a first group of fin structures having a first pitch and a second group of fin structures having a second pitch.
19. The semiconductor device of claim 18 , wherein the dielectric spacer is self-aligned to a central position of the first pitch and second pitch.
20. The semiconductor device of claim 19 , wherein the first pitch is greater than the second pitch, and the dielectric spacer between adjacent semiconductor fin structures in the first group having the first pitch has a width that is greater than the dielectric spacer between adjacent semiconductor fin structures in the second group having the second pitch.