Method, system and device for recessed contact in memory array
Embodiments disclosed herein may relate to forming a contact region for an interconnect between a selector transistor and a word-line electrode in a memory device.
1. A method, comprising:
forming one or more recessed word-line contact regions in a first material of a phase change memory array, including performing a pitch multiplication operation, wherein the pitch multiplication operation provides a pattern interruption to create one or more recessed word-line contact regions.
2. The method of claim 1 , wherein forming the one or more recessed word-line contact regions comprises forming buried n+ silicon word-line contact regions.
3. A method, comprising:
forming one or more recessed word-line contact regions in a first material of a phase change memory array, including performing a pitch multiplication operation, wherein performing the pitch multiplication operation comprises conducting a self-aligned double-patterning operation on a stack of semiconductor layers including the first material over a substrate material, the first material having an opposite conductivity type from the substrate material, and a second material over the first material, wherein the second material has the conductivity type of the substrate material.
4. The method of claim 1 , wherein providing the pattern interruption creates a space between a pair of selector transistors that is greater than two times a width of one of the selector transistors in the phase change memory array.
5. The method of claim 4 , wherein the space is greater than four times the width of the one of the selector transistors.
6. The method of claim 5 , wherein the performing the pitch multiplication operation comprises defining a plurality of the selector transistors each having an emitter and forming a phase change memory storage component over each emitter.
7. The method of claim 1 , wherein the performing the pitch multiplication operation comprises patterning one or more word-line strings in a stack of semiconductor layers, wherein the one or more word-line strings individually comprise a collector component comprising a substrate material, a base component, and an emitter component, and wherein the one or more word-line strings are oriented in a word-line direction.
8. The method of claim 7 , wherein the performing the pitch multiplication operation further comprises depositing a dielectric material over the one or more word-line strings.
9. The method of claim 8 , wherein the performing the pitch multiplication operation further comprises creating one or more pairs of lines over the dielectric material.
10. The method of claim 9 , wherein creating the one or more pairs of lines over the dielectric material comprises spacing two of the one or more pairs of lines apart by a distance of approximately greater than four times a width of a phase change memory storage component.
11. The method of claim 10 , wherein the performing the pitch multiplication operation further comprises forming sidewall spacers on the one or more pairs of lines.
12. The method of claim 11 , wherein the performing the pitch multiplication operation further comprises transferring a pattern of the sidewall spacers into the dielectric material.
13. The method of claim 12 , wherein the performing the pitch multiplication operation further comprises transferring the pattern of the sidewall spacers into the one or more word-line strings.
14. The method of claim 1 , wherein forming the one or more recessed word-line contact regions in the first material comprises forming trenches to insulate memory cells of the phase change memory array.
15. The method of claim 4 , wherein the selector transistors are bipolar junction transistors.
16. The method of claim 6 , wherein the plurality of the selector transistors comprises a common cathode component.
17. The method of claim 6 , wherein the word-line contact regions are recessed relative to the emitters.
18. The method of claim 11 , wherein forming the sidewall spacers comprises:
depositing a conformal spacer layer on the one or more pairs of lines; and
directionally etching the conformal spacer layer to define the sidewall spacers.
19. The method of claim 18 , wherein the conformal spacer layer comprises silicon oxide.