IP Library › Granted Patent US 9,658,664
Granted Patent B2
US 9,658,664 · App. 14/395,730 · Granted May 23, 2017

Electronic device having a pin for setting its mode of operation and method to set a mode of operation for an electronic device having a pin

Inventors: Valerie Bernon-Enjalbert (Fonsorbes, FR); Philippe Mounier (Tournefeuille, FR); Franck Galtie (Plaisance du Touch, FR)
Assignee: NXP USA, Inc.
G06F1/24G06F1/26G06F11/3656
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,658,664
App. No.
14/395,730
Granted
May 23, 2017
Kind
B2
Abstract

An electronic device having a pin for setting its mode of operation, wherein the pin is connected or connectable to a first connection of a resistor, wherein the electronic device is arranged to detect a location of the resistor, wherein the electronic device is arranged to detect a size of the resistor, wherein the electronic device is arranged to determine a first setting based on the location of the resistor, and wherein the electronic device is arranged to determine a second setting based on the size of the resistor.

Claims (47)

1. An electronic device having a pin for setting its mode of operation, the electronic device comprising:

a push-pull stage including a first transistor having a first current electrode coupled to the pin and a second current electrode coupled to a first reference voltage and a second transistor having a first current electrode coupled to the pin and a second current electrode coupled to a second reference voltage, the push-pull stage configured to adjust a voltage provided at the pin;

a first current mirror including a third transistor, a control electrode of the third transistor coupled to a control electrode of the first transistor, the first current mirror to clone a current conducted at the first transistor; and

a second current mirror including a fourth transistor, a control electrode of the fourth transistor coupled to a control electrode of the second transistor, the second current mirror to clone a current conducted at the second transistor,

wherein the pin is connected to a first terminal of a resistor,

wherein the electronic device is arranged to detect a location of the resistor, the location identifying connectivity of a second terminal of the resistor,

wherein the electronic device is arranged to detect a size of the resistor based on a current provided by the first current mirror and a current provided by the second current mirror,

wherein the electronic device is arranged to determine a first setting based on the location of the resistor, and

wherein the electronic device is arranged to determine a second setting based on the size of the resistor.

2. The electronic device as claimed in claim 1 ,

wherein the electronic device is arranged to detect the location of the resistor based on a sensed first internal current and a sensed second internal current,

wherein the sensed first internal current flows between a voltage supply pin of the electronic device and the pin, and wherein the sensed second internal current flows concurrent with the first internal current between the pin and a ground pin of the electronic device.

3. The electronic device as claimed in claim 2 , wherein the electronic device is arranged to generate a first signal for the first setting based on a sign of a difference between the sensed first internal current and the sensed second internal current.

4. The electronic device as claimed in claim 2 , wherein the electronic device is arranged to generate a second signal for the second setting based on an absolute value of a difference between the sensed first internal current and the sensed second internal current.

5. The electronic device as claimed in claim 4 , wherein the electronic device is arranged to detect the absolute value of the difference between the sensed first internal current and the sensed second internal current In by a comparison with at least one reference current source.

6. The electronic device as claimed in claim 1 , wherein the first setting is related to a debug mode.

7. The electronic device as claimed in claim 1 , wherein the second setting is related to a hardware configuration.

8. A method to set a mode of operation for an electronic device having a pin connected to a first terminal of a resistor, the method comprising:

generating a first current conducted between a first current electrode and a second current electrode of a first transistor of a push pull circuit, the first current electrode coupled to the pin and a second current electrode coupled to a first reference voltage;

generating a second current conducted between a first current electrode and a second current electrode of a second transistor of the push pull circuit, the second transistor having a first current electrode coupled to the pin and a second current electrode coupled to a second reference voltage, the push-pull stage configured to adjust a voltage provided at the pin;

cloning the first current at a first current mirror, the first current mirror including a third transistor, a control electrode of the third transistor coupled to a control electrode of the first transistor; and

cloning the second current at a second current mirror, the second current mirror including a fourth transistor, a control electrode of the fourth transistor coupled to a control electrode of the second transistor;

wherein the electronic device detects a location of the resistor, the location identifying connectivity of a second terminal of the resistor,

wherein the electronic device detects a size of the resistor based on the cloned first current and the cloned second current,

wherein the electronic device determines a first setting based on the location of the resistor, and

wherein the electronic device determines a second setting based on the size of the resistor.

9. The method as claimed in claim 8 ,

wherein the electronic device detects the location of the resistor based on a sensed first internal current and a sensed second internal current,

wherein the sensed first internal current flows between a voltage supply pin and the pin, and wherein the sensed second internal current flows between the pin and a ground pin.

10. The method as claimed in claim 9 , wherein the electronic device generates a first signal for the first setting based on the sign of a difference between the sensed first internal current and the sensed second internal current.

11. The method as claimed in claim 9 , wherein the electronic device generates a second signal for the second setting based on an absolute value of a difference between the sensed first internal current and the sensed second internal current.

12. The method as claimed in claim 11 , wherein the electronic device detects the absolute value of the difference between the sensed first internal current and the sensed second internal current by a comparison with at least one reference current source.

13. The method as claimed in claim 8 , wherein the first setting is related to a debug mode.

14. The method according to claim 8 , wherein the second setting is related to a hardware configuration.

15. An electronic device having a pin for setting its mode of operation, the electronic device comprising:

wherein the pin is connected to a first terminal of a resistor,

wherein the electronic device is arranged to detect a location of the resistor, the location identifying connectivity of a second terminal of the resistor,

wherein the electronic device is arranged to detect a size of the resistor,

wherein the electronic device is arranged to determine a first setting based on the location of the resistor,

wherein the electronic device is arranged to determine a second setting based on the size of the resistor,

wherein the electronic device is arranged to detect the location of the resistor based on a sensed first internal current and a sensed second internal current,

wherein the sensed first internal current flows between a voltage supply pin of the electronic device and the pin, and wherein the sensed second internal current flows concurrent with the first internal current between the pin and a ground pin of the electronic device.

16. The electronic device as claimed in claim 15 , wherein the electronic device is arranged to generate a first signal for the first setting based on a sign of a difference between the sensed first internal current and the sensed second internal current.

17. The electronic device as claimed in claim 15 , wherein the electronic device is arranged to generate a second signal for the second setting based on an absolute value of a difference between the sensed first internal current and the sensed second internal current.

18. The electronic device as claimed in claim 17 , wherein the electronic device is arranged to detect the absolute value of the difference between the sensed first internal current and the sensed second internal current In by a comparison with at least one reference current source.

19. The electronic device as claimed in claim 15 , wherein the first setting is related to a debug mode.

20. The electronic device as claimed in claim 1 , wherein the second setting is related to a hardware configuration.

Assignments (24)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0535 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0444 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037358/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035034/0019 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0923 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 20, 2014
From: BERNON-ENJALBERT, VALERIE; GALTIE, FRANCK; MOUNIER, PHILIPPE
To: FREESCALE SEMICONDUCTOR INC.
Reel/Frame 033984/0063 →
Continuity (1)
Related Publication 20150082017A1 · Mar 19, 2015