Method and apparatus for timing adjustment
A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section.
1. A data latch timing adjustment apparatus for receiving m external strobe signals and m groups of external data in synchronism with the m external strobe signals respectively, where m is an integer greater than or equal to 2, the apparatus comprising:
m sets of a data delay selection section, a strobe latch section and a system latch section; and
at least one clock delay selection section generating a clock for the system latch section,
wherein each set of the m sets is associated with one of the m external strobe signals respectively,
wherein the data delay selection section delays one group of the m groups of the external data,
wherein the strobe latch section latches data from the data delay selection section, and
wherein the system latch section latches data from the strobe latch section with the clock from the clock delay selection section.
2. The data latch timing adjustment apparatus of claim 1 , wherein the clock delay selection section includes:
a PLL; and
a variable delay section including a series of delay circuits, wherein the variable delay section receives an output from the PLL and outputs the clock.
3. The data latch timing adjustment apparatus of claim 1 , wherein each of the m sets of the data delay selection section, the strobe latch section and the system latch section further includes:
a strobe delay selection section delaying the external strobe signal for adjusting timing between the external strobe signal and the one group of the m groups of the external data.