Semiconductor structure including a nonvolatile memory cell and method for the formation thereof

1. A method, comprising:

providing a semiconductor structure comprising a semiconductor material;

forming a layer of a floating gate material that is surrounded by at least one electrically insulating material over said semiconductor material;

forming a gate stack over said semiconductor structure;

patterning said gate stack, said patterning of said gate stack forming a select gate, said select gate comprising a first portion and a second portion, wherein said first portion of said select gate is provided over a portion of said semiconductor material adjacent to said layer of floating gate material and said second portion of said select gate is provided over a portion of said layer of floating gate material adjacent to said first portion of said select gate; and

after said patterning of said gate stack, forming a control gate insulation layer above at least a portion of said select gate and forming a control gate material above said control gate insulation layer to define a control gate over a portion of said layer of floating gate material.

2. The method of claim 1 , wherein said forming of said layer of floating gate material that is surrounded by said at least one electrically insulating material comprises:

forming a first electrically insulating layer over said semiconductor material;

depositing said layer of said floating gate material over said first electrically insulating layer;

forming a second electrically insulating layer over said layer of said floating gate material;

patterning said first electrically insulating layer, said layer of said floating gate material and said second electrically insulating layer, wherein a sidewall of said layer of said floating gate material is formed; and

forming an electrical insulation at said sidewall of said layer of said floating gate material.

3. The method of claim 2 , wherein said forming of said electrical insulation at said sidewall of said layer of said floating gate material comprises:

forming a third electrically insulating layer over said semiconductor structure; and

performing an anisotropic etch process adapted to remove a material of said third electrically insulating layer, wherein a portion of said third electrically insulating layer at said sidewall of said layer of said floating gate material remains in said semiconductor structure and forms a sidewall spacer at said sidewall of said layer of floating gate material, said sidewall spacer providing said electrical insulation.

4. The method of claim 3 , wherein said gate stack comprises a layer of a gate insulation material having a dielectric constant that is greater than a dielectric constant of silicon and a metal layer over said layer of gate insulation material.

5. The method of claim 4 , wherein said patterning of said gate stack additionally forms a gate of a logic transistor from said gate stack.

6. The method of claim 5 , wherein said gate stack further comprises a polysilicon layer over said metal layer.

7. The method of claim 6 , further comprising:

after said patterning of said gate stack, forming an encapsulation layer over said semiconductor structure, said encapsulation layer comprising a portion at a sidewall of said select gate.

8. The method of claim 7 , wherein said forming of said encapsulation layer comprises performing a molecular layer deposition of silicon nitride.

9. The method of claim 8 , further comprising:

providing a floating gate on the basis of said layer of floating gate material;

forming a source region on a side of said floating gate opposite said select gate; and

forming a drain region on a side of said select gate opposite said floating gate.

10. The method of claim 9 , further comprising forming an erase gate over said source region.

11. A method, comprising:

providing a semiconductor structure comprising a semiconductor material;

forming a layer stack comprising one or more electrically insulating layers and a layer of floating gate material over a first portion of said semiconductor material;

forming a sidewall spacer comprising an electrically insulating material at a sidewall of said layer stack;

after said forming of said sidewall spacer, forming a gate stack over said semiconductor structure;

patterning said gate stack, said patterning of said gate stack forming a select gate, wherein at least a first portion of said select gate is provided over a second portion of said semiconductor material adjacent to said layer stack; and

after said patterning of said gate stack, forming a control gate insulation layer above at least a portion of said select gate and forming a control hate material above said control gate insulation layer to define a control gate over a portion of said layer of floating gate material.

12. The method of claim 11 , wherein said sidewall spacer comprises silicon dioxide.

13. The method of claim 12 , wherein said select gate further comprises a second portion provided over a portion of said layer stack that is adjacent to said first portion of said select gate.

14. The method of claim 1 , further comprising:

forming a source region on a side of said floating gate opposite said select gate;

forming a drain region on a side of said select gate opposite said floating gate;

forming an erase gate over said source region, wherein a cavity is defined between the erase gate and the select gate; and

forming said control gate in said cavity.

15. The method of claim 11 , further comprising:

forming a source region on a side of said floating gate opposite said select gate;

forming a drain region on a side of said select gate opposite said floating gate;

forming an erase gate over said source region, wherein a cavity is defined between the erase gate and the select gate; and

forming said control gate in said cavity.