Granted Patent B2

US 9,727,684 · App. 14/633,477 · Granted Aug 8, 2017

Inventors: Hongwei Dai (Shanghai, CN); Jifeng Li (Beijing, CN); Jia Niu (Shanghai, CN); Yu Yun Song (Shanghai, CN)

Assignee: GLOBALFOUNDRIES INC.

G06F17/5081G06F17/5072G06F17/504G06F17/5031G06F17/5068G06F2217/84

Abstract

Claims (33)

1. A method for fixing a hold time violation in a circuit, comprising:

identifying the hold time violation in the circuit;

creating a topology diagram of the circuit, a branch in the topology diagram indicating a signal path where the identified hold time violation occurs in the circuit, and a node on the branch indicating a port of an element where the identified hold time violation occurs in the signal path;

dividing the circuit into a plurality of regions; and

placing a hold time correction element selectively in an identified region corresponding to the node in the topology diagram to fix the hold time violation of the node, according to a circuit element density of the identified region,

wherein the placing comprises:

creating a node list which includes all nodes in the topology diagram having fixable hold time violations, the respective nodes in the node list being ranked according to numbers of input paths and output paths and hold slacks of the respective nodes in the node list;

for each node in the node list, identifying in the topology diagram, from the plurality of regions, a region corresponding to the node; and

placing hold time correction elements selectively in the identified regions corresponding to the nodes in the node list, to fix the hold time violations thereof, according to circuit element densities of the identified regions corresponding to the respective nodes in the node list, in an order of the respective nodes in the node list.

2. The method of claim 1 , wherein the placing a hold time correction element selectively in an identified region corresponding to the node in the topology diagram to fix the hold time violation of the node, according to a circuit element density of the identified region includes:

comparing the circuit element density of the identified region corresponding to the node with a density threshold; and

placing the hold time correction element in the identified region corresponding to the node to fix the hold time violation thereof, in response to determining that the circuit element density of the region corresponding to the node does not exceed the density threshold.

3. The method of claim 1 , wherein the placing a hold time correction element selectively in an identified region corresponding to the node in the topology diagram to fix the hold time violation of the node, according to a circuit element density of the identified region further includes:

removing, from the node list, the node where the hold time violation has been fixed and nodes on a same signal path as the node.

4. The method of claim 3 , wherein the placing a hold time correction element selectively in an identified region corresponding to the node in the topology diagram to fix the hold time violation according to a circuit element density of the identified region further includes:

selecting, for a rest node where hold time violation can be fixed in the node list, a region which surrounds a region corresponding to the rest node and whose circuit element density do not exceed the density threshold;

placing a hold time correction element chain in the selected region to fix the hold time violation at the rest node, the hold time correction element chain including at least one hold time correction element placed in the selected region and at least one driving element connecting the at least one hold time correction element with the rest node.

5. The method of claim 4 , wherein the placing a hold time correction element chain in the selected region to fix the hold time violation at the rest node includes:

selecting a type of the hold time correction element chain according to a setup slack and a hold slack at the rest node, and

placing the selected type of hold time correction element chain in the selected region to fix the hold time violation at the rest nodes.

6. An apparatus for fixing a hold time violation in a circuit, comprising:

a hold time violation identification device, configured to identify the hold time violation in the circuit;

a topology diagram creating device, configured to create a topology diagram of the circuit, a branch in the topology diagram indicating a signal path where the hold time violation identified by the hold time violation identification device occurs in the circuit, and a node on the branch indicating a port of an element where the hold time violation identified by the hold time violation identification device occurs in the signal path;

a circuit dividing device, configured to divide the circuit into a plurality of regions;

a violation fixing device, configured to place a hold time correction element selectively in an identified region corresponding to the node in the topology diagram to fix the hold time violation of the node, according to a circuit element density of the identified region,

wherein the violation fixing device includes:

a list creating unit configured to create a node list which includes all nodes in the topology diagram having fixable hold time violations, the respective nodes in the node list being ranked according to numbers of input paths and output paths and hold slacks of the respective nodes in the node list;

an identifying unit configured to for each node in the node list created by the list creating unit, identify in the topology diagram, from the plurality of regions, a region corresponding to the node; and

a fixing unit configured to selectively place hold time correction elements in the identified regions corresponding to the nodes in the node list, to fix the hold time violations thereof, according to circuit element densities of the identified regions corresponding to the respective nodes in the node list, in an order of the respective nodes in the node list.

7. The apparatus of claim 6 , wherein the violation fixing device is configured to compare the circuit element density of the identified region with a density threshold, and place the hold time correction element in the identified region fix the hold time violation of the node, in response to determining that the circuit element density of the identified region does not exceed the density threshold.

8. The apparatus of claim 7 , wherein the fixing unit is further configured to remove, from the node list, the node where the hold time violation has been fixed and nodes on a same signal path as the node.

9. The apparatus of claim 8 , wherein the fixing unit is further configured to select, for a rest node where hold time violation can be fixed in the node list, a region which surrounds a region corresponding to the rest node and whose circuit element density do not exceed the density threshold, and place a hold time correction element chain in the selected region to fix the hold time violation at the rest node, the hold time correction element chain including at least one hold time correction element placed in the selected region and at least one driving element connecting the at least one hold time correction element with the rest node.

10. The apparatus of claim 9 , wherein the fixing unit is configured to place a hold time correction element chain in the selected region to fix the hold time violation at the rest node by selecting a type of the hold time correction element chain according to a setup slack and a hold slack at the rest node, and placing the selected type of hold time correction element chain in the selected region to fix the hold time violation at the rest nodes.

Assignments (9)

Priority Claims (1)

Continuity (1)