IP Library › Granted Patent US 9,739,669
Granted Patent B2
US 9,739,669 · App. 14/097,405 · Granted Aug 22, 2017

Temperature sensor peripheral having independent temperature coefficient and offset adjustment programmability

Inventors: David Michael Susak (Chandler, AZ); Raghuveer Murukumpet (Bangalore, IN)
Assignee: MICROCHIP TECHNOLOGY INCORPORATED
G01K15/005G01K7/01G01K7/21
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Quick Facts
Patent No.
US 9,739,669
App. No.
14/097,405
Granted
Aug 22, 2017
Kind
B2
Abstract

A temperature sensor peripheral generates an output voltage that is proportional to temperature, whose temperature coefficient can be adjusted to any desired value, whose temperature coefficient can be either positive or negative, whose room temperature voltage can be adjusted to any desired value, and whose temperature coefficient and room temperature voltage adjustments are independent from one another.

Claims (43)

1. A circuit arrangement for measuring a temperature and producing a voltage representative thereof, comprising:

first and second voltage-to-current converters each having a single voltage input, a current adjust input and a current output;

a first operational amplifier having first and second inputs and an output;

a first programmable resistor coupled to the current adjust input of the first voltage-to-current converter, wherein the first resistor adjusts a value of a first current from the current output thereof;

a second programmable resistor coupled to the current adjust input of the second voltage-to-current converter, wherein the second resistor adjusts a value of a second current from the current output thereof;

a third resistor coupled between the output and the second input of the first operational amplifier;

the outputs of the first and second voltage-to-current converters and the second input of the first operational amplifier are coupled together;

a first reference voltage coupled to the voltage input of the first voltage-to-current converter;

a second reference voltage coupled to the voltage input of the second voltage-to-current converter;

a third reference voltage provided by a digital to analog converter (DAC), wherein the third reference voltage is coupled to the first input of the operational amplifier;

wherein a third current through the third resistor is equal to the second current minus the first current.

2. The circuit arrangement according to claim 1 , wherein the first input of the first operational amplifier is a positive input and the second input thereof is a negative input.

3. The circuit arrangement according to claim 1 , wherein an output voltage from the first operational amplifier is defined by:

Vref3

+

R3

R2

⁢

Vref2

-

R3

R1

⁢

Vref1

,

wherein Vref 1 , Vref 2 , Vref 3 represent a value of the first, second and third reference voltage, respectively, and R 1 , R 2 , and R 3 represent a value of the first, second and third resistor.

4. The circuit arrangement according to claim 1 , wherein the first reference voltage is provided by an external temperature sensor having a voltage output proportional to a temperature thereof, and the second and third reference voltages are from fixed voltage references having substantially zero temperature coefficients.

5. The circuit arrangement according to claim 1 , wherein the second resistor is adjusted so that a voltage from the output of the first operational amplifier is equal to the third reference voltage, and the second current is equal to the first current.

6. The circuit arrangement according to claim 1 , further comprising a digital processor configured to adjust a resistance of the first and second programmable resistor and to adjust the third reference voltage by controlling the DAC.

7. The circuit arrangement according to claim 1 , wherein the third resistor is a programmable resistor.

8. The circuit arrangement according to claim 7 , further comprising a digital processor configured to adjust a resistance of the first, second, and third programmable resistor and to adjust the third reference voltage by controlling the DAC.

9. The circuit arrangement according to claim 1 , wherein the first and second voltage-to-current converters are provided by

a second operational amplifier, and

first and second transistors having sources coupled together, gates coupled to an output of the second operational amplifier, and drains coupled to the first and second resistors.

10. The circuit arrangement according to claim 9 , wherein the second and third reference voltages are from the same voltage reference.

11. The circuit arrangement according to claim 1 , wherein:

the first reference voltage is from a temperature sensor,

the third reference voltage and the second resistor value determine a first output voltage representing a first calibration temperature, and

the third resistor value determines a second output voltage representing a second calibration temperature.

12. The circuit arrangement according to claim 11 , wherein the first calibration temperature is room temperature.

13. The circuit arrangement according to claim 11 , wherein the temperature sensor is a semiconductor diode providing a diode junction voltage as a function of temperature.

14. The circuit arrangement according to claim 11 , wherein the temperature sensor is a resistance temperature detector.

15. The circuit arrangement according to claim 11 , wherein the temperature sensor is a thermistor.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 059666/0545 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: MICROCHIP TECHNOLOGY INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041675/0617 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 12, 2014
From: SUSAK, DAVID MICHAEL; MURUKUMPET, RAGHUVEER
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 032207/0790 →
Continuity (2)
Provisional Application 61735243 · Dec 10, 2012
Related Publication 20140161149A1 · Jun 12, 2014