Uniform thickness blocking dielectric portions in a three-dimensional memory structure

1. A method of manufacturing a three-dimensional memory device, comprising:

forming a stack of alternating layers comprising first material layers and second material layers over a substrate;

forming a memory opening through the stack;

laterally recessing sidewall surfaces of the second material layers with respect to sidewall surfaces of the first material layers within the memory opening;

forming annular semiconductor material portions by depositing a semiconductor material from the sidewall surfaces of the second material layers while the semiconductor material does not grow from surfaces of the first material layers;

forming a memory film over inner surfaces of the annular semiconductor material portions.

2. The method of claim 1 , further comprising:

forming backside recesses by removing the second material layers selective to the first material layers; and

forming electrically conductive layers in the backside recesses.

3. The method of claim 2 , further comprising removing at least an outer portion of each of the annular semiconductor material portions after removing the second material layers.

4. The method of claim 1 , wherein the second material layers are removed employing an etch chemistry that is selective to the semiconductor material of the annular semiconductor material portions.

5. The method of claim 1 , further comprising converting an inner portion of each annular semiconductor portion into an annular dielectric material portion that includes a dielectric material, wherein each remaining annular semiconductor material portion comprises the semiconductor material.

6. The method of claim 5 , further comprising:

forming backside recesses by removing the second material layers selective to the first material layers; and

removing the remaining annular semiconductor material portions selective to the annular dielectric material portions.

7. The method of claim 1 , wherein forming the memory film comprises forming a blocking dielectric layer on the inner surfaces of the annular semiconductor material portions, and the method further comprises removing the semiconductor material of the annular semiconductor material portions employing another etch chemistry that is selective to a material of the blocking dielectric layer.

8. The method of claim 1 , wherein:

the first material layers comprise silicon oxide layers and the second material layers comprise silicon nitride layers; and

the annular semiconductor material portions are formed by a selective deposition process.

9. The method of claim 8 , wherein a semiconductor precursor gas and an etchant gas are flowed into a process chamber including a combination of the substrate and the stack concurrently or alternately during the selective deposition process.

10. The method of claim 8 , wherein the sidewall surfaces of the second material layers are laterally recessed with respect to the sidewall surfaces of the first material layers employing an isotropic etch chemistry.

11. The method of claim 1 , wherein forming the memory film comprises:

forming a blocking dielectric layer over the annular semiconductor material portions;

forming at least one charge storage element on the blocking dielectric layer; and

forming a tunneling dielectric on the at least one charge storage element.

12. The method of claim 1 , wherein:

the three-dimensional memory device comprises a vertical NAND device;

portions of the second material layers are replaced with electrically conductive layers; and

at least one of the electrically conductive potions in the stack comprises, or is electrically connected to, a word line of the vertical NAND device.

13. The method of claim 12 , wherein:

the vertical NAND device comprises:

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;

the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level;

the electrically conductive portions in the stack comprise, or are in electrical contact with, the plurality of control gate electrodes and extend from the device region to a contact region containing the plurality of electrically conductive via connections; and

the substrate comprises a silicon substrate containing a driver circuit for the vertical NAND device.