IP Library Granted Patent US 9,761,720
Granted Patent B2
US 9,761,720 · App. 14/954,166 · Granted Sep 12, 2017

Replacement body FinFET for improved junction profile with gate self-aligned junctions

Inventor: Viorel Ontalus (Unionville, CT)
Assignee: GLOBALFOUNDRIES INC.
H01L29/7848H01L29/0847H01L29/6681H01L29/66545H01L29/66795H01L29/7851
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,761,720
App. No.
14/954,166
Granted
Sep 12, 2017
Kind
B2
Abstract

After forming an epitaxial semiconductor layer on portions of a semiconductor located on opposite sides of a sacrificial gate structure, dopants from the epitaxial semiconductor layer are diffused into the semiconductor fin to form a dopant-containing semiconductor fin. A sacrificial gate stack is removed to provide a gate cavity that exposes a portion of the dopant-containing semiconductor fin. The exposed portion of the dopant-containing semiconductor fin is removed to provide an opening underneath the gate cavity. A channel which is undoped or less doped than remaining portions of the dopant-containing semiconductor fin is epitaxially grown at least from the sidewalls of the remaining portions of the dopant-containing semiconductor fin. Abrupt junctions are thus formed between the channel region and the remaining portions of the dopant-containing semiconductor fin.

Claims (31)

1. A method of forming a semiconductor structure comprising:

forming a sacrificial gate structure over a portion of a semiconductor fin, the sacrificial gate structure comprising a sacrificial gate stack and a gate spacer present on sidewalls of the sacrificial gate stack;

forming an epitaxial semiconductor layer comprising dopants of a first conductivity type over portions of the semiconductor fin that is not covered by the sacrificial gate structure;

forming a dopant-containing semiconductor fin by diffusing the dopants from the epitaxial semiconductor layer into the semiconductor fin, wherein a dopant concentration profile across the dopant-containing semiconductor fin is graded such that a portion of the dopant-containing semiconductor fin underneath the sacrificial gate stack has a lower dopant concentration than another portion of the dopant-containing semiconductor fin;

removing the sacrificial gate stack to form a gate cavity exposing a portion of the dopant-containing semiconductor fin;

removing the exposed portion of the dopant-containing semiconductor fin to provide an opening underneath the gate cavity, wherein the removing the exposed portion of the dopant-containing semiconductor fin removes an entirety of the exposed portion of the dopant-containing semiconductor fin to expose a top surface of a semiconductor substrate;

forming a channel region in the opening, wherein the forming the channel region is performed by epitaxially growing a semiconductor material from sidewalls of portions of the dopant-containing semiconductor fin that are covered by the gate spacer and the top surface of the semiconductor substrate; and

forming a functional gate stack in the gate cavity over the channel region.

2. The method of claim 1 , wherein the forming the dopant-containing semiconductor fin is performed by an anneal process.

3. The method of claim 1 , wherein the another portion of the dopant-containing semiconductor fin extends beyond inner sidewalls of the gate spacer and underneath peripheral portions of the sacrificial gate stack.

4. The method of claim 1 , wherein after the removing the exposed portion of the dopant-containing semiconductor fin, remaining portions of the dopant-containing semiconductor fin that are covered by the sacrificial gate structure have sidewalls vertically coincident with inner sidewalls of the gate spacer.

5. The method of claim 1 , further comprising forming a sacrificial spacer on sidewalls of the exposed portion of the dopant-containing semiconductor fin prior to the removing the exposed portion of the dopant-containing semiconductor fin.

6. The method of claim 5 , further comprising removing the sacrificial spacer after the forming the channel region.

7. The method of claim 1 , wherein the channel region is undoped or doped with dopants of a second conductivity type opposite to the first conductivity type.

8. A method of forming a semiconductor structure comprising:

forming a sacrificial gate structure over a portion of a semiconductor fin, the sacrificial gate structure comprising a sacrificial gate stack and a gate spacer present on sidewalls of the sacrificial gate stack;

forming an epitaxial semiconductor layer comprising dopants of a first conductivity type over portions of the semiconductor fin that is not covered by the sacrificial gate structure;

forming a dopant-containing semiconductor fin by diffusing the dopants from the epitaxial semiconductor layer into the semiconductor fin, wherein a dopant concentration profile across the dopant-containing semiconductor fin is graded such that a portion of the dopant-containing semiconductor fin underneath the sacrificial gate stack has a lower dopant concentration than another portion of the dopant-containing semiconductor fin;

removing the sacrificial gate stack to form a gate cavity exposing a portion of the dopant-containing semiconductor fin;

removing the exposed portion of the dopant-containing semiconductor fin to provide an opening underneath the gate cavity, wherein the removing the exposed portion of the dopant-containing semiconductor fin removes an entirety of the exposed portion of the dopant-containing semiconductor fin to expose a top surface of a buried insulator layer;

forming a channel region in the opening, wherein the forming the channel region is performed by epitaxially growing a semiconductor material from sidewalls of portions of the dopant-containing semiconductor fin that are covered by the gate spacer; and

forming a functional gate stack in the gate cavity over the channel region.

9. A method of forming a semiconductor structure comprising:

forming a sacrificial gate structure over a portion of a semiconductor fin, the sacrificial gate structure comprising a sacrificial gate stack and a gate spacer present on sidewalls of the sacrificial gate stack;

forming an epitaxial semiconductor layer comprising dopants of a first conductivity type over portions of the semiconductor fin that is not covered by the sacrificial gate structure;

forming a dopant-containing semiconductor fin by diffusing the dopants from the epitaxial semiconductor layer into the semiconductor fin, wherein a dopant concentration profile across the dopant-containing semiconductor fin is graded such that a portion of the dopant-containing semiconductor fin underneath the sacrificial gate stack has a lower dopant concentration than another portion of the dopant-containing semiconductor fin;

removing the sacrificial gate stack to form a gate cavity exposing a portion of the dopant-containing semiconductor fin;

removing the exposed portion of the dopant-containing semiconductor fin to provide an opening underneath the gate cavity, wherein the removing the exposed portion of the dopant-containing semiconductor fin removes an outer portion of the exposed portion of the dopant-containing semiconductor fin, leaving an interior portion of the exposed portion of the dopant-containing semiconductor fin intact, wherein the interior portion is a least doped portion in the dopant-containing semiconductor fin;

forming a channel region in the opening, wherein the forming the channel region is performed by epitaxially growing a semiconductor material from sidewalls of portions of the dopant-containing semiconductor fin that are covered by the sacrificial gate stack and the interior portion of the exposed portion of the dopant-containing semiconductor fin; and

forming a functional gate stack in the gate cavity over the channel region.

10. The method of claim 9 , wherein the outer portion of the exposed portion of the dopant-containing semiconductor fin is removed by an isotropic etch.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2020
From: GLOBALFOUNDRIES INC.
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 054633/0001 →
SECURITY AGREEMENT Recorded Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 30, 2015
From: ONTALUS, VIOREL
To: GLOBALFOUNDRIES INC.
Reel/Frame 037168/0407 →
Continuity (1)
Related Publication 20170154995A1 · Jun 1, 2017