IP Library Granted Patent US 9,836,379
Granted Patent B2
US 9,836,379 · App. 14/397,189 · Granted Dec 5, 2017

Method and system for generating a memory trace of a program code executable on a programmable target

Inventors: Dragos Badea (Bucharest, RO); Andrei Mihaila (Bucharest, RO)
Assignee: NXP USA, Inc.
G06F11/3471G06F11/3636G06F11/3644G06F2201/865G06F2201/88
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Quick Facts
Patent No.
US 9,836,379
App. No.
14/397,189
Granted
Dec 5, 2017
Kind
B2
Abstract

A method of generating an instrumented code from a program code executable on a programmable target is described. The method comprises analyzing the program code to detect a loop nest with regular memory access in the program code, providing a record of static memory address information associated with the loop nest, and instrumenting the program code to provide an instrumented code corresponding to the program code supplemented with an instrumentation instruction to output an information message comprising a dynamic memory address information field formatted to store a dynamic memory address information associated with the loop nest.

Claims (57)

1. A method comprising:

analyzing, by an instrumentation module stored on a computer readable storage medium to be executed by a programmable processor coupled to the computer readable storage medium, a program code for a target processor to detect a loop nest of the program code having regular memory access and a location of the detected loop nest in the program code, wherein a loop nest is associated with an instruction address and includes a loop iteration variable indicating a number of iterations of the loop nest;

determining, by the instrumentation module, a memory access pattern of the loop nest based on memory access instructions in the loop nest;

providing, based on the analyzing, a record of a static memory address information associated with the loop nest, wherein providing the record of the static memory address information associated with the loop nest includes:

generating a memory access pattern function describing the memory address pattern of the loop nest by a start address of the memory access pattern of the loop nest and the loop iteration variable,

generating memory access pattern parameters representing the instruction address and a size of a memory access based on the loop iteration variable, and

generating the static memory address information from the memory access pattern function and the memory access pattern parameters;

instrumenting, by the instrumentation module, the program code to provide an instrumented code for the target processor comprising the program code supplemented with an instrumentation instruction inserted at an entry position of the detected loop nest based on the location of the detected loop nest, the instrumentation instruction to be executed only once per instantiation of the loop nest and to output an information message during runtime by the target processor that comprises a dynamic memory address information field formatted to store a dynamic memory address information associated with the loop nest that indicates a runtime value of a start address of the memory access pattern of the loop nest based on the loop nest and the memory access pattern of the loop nest, wherein the information message is based on the record of the static memory address information; and

storing and compiling, by the target processor, the instrumented code for the target processor for executing the instrumented code to generate a memory trace for the loop nest.

2. The method according to claim 1 , wherein

the dynamic memory address information field is further formatted to store in respective information fields a runtime value of an instruction address related to the loop nest, the runtime value of the start address of the memory access pattern of the loop nest, and a runtime value of an iteration count of loop variables of the loop nest.

3. The method of claim 1 further comprising:

compiling, by the programmable processor, the instrumented code to obtain an instrumented executable program for execution by the target processor;

loading, by a linker executed by the programmable processor, the instrumented executable program in the target processor;

storing, by the instrumented executable program executed by the target processor, the dynamic memory address information in the dynamic memory address information fields of the information message;

sending, by the instrumented executable program, the information message to the programmable processor;

receiving, by an information collector stored on the computer readable storage medium executed by the programmable processor, the information message from the target processor;

extracting, by the information collector, the dynamic address information from the information message;

collecting, by the information collector, the dynamic memory address information to obtain a record of the dynamic memory address information; and

generating, by a memory trace combiner stored on the computer readable storage medium executed by the programmable processor, the memory trace of the program code executable based on the record of static memory address information and the record of the dynamic address information.

4. A computer program product comprising instructions for causing the processor system to perform a method comprising:

obtaining, by an information collector stored on the computer readable storage medium executed by the programmable processor, the record of static memory address information associated with the loop nest provided by the method according to claim 1 ;

receiving, by the information collector, the information message from the target processor;

extracting, by the information collector, the dynamic address information from the information message;

collecting, by the information collector, the dynamic address information to obtain a record of the dynamic address information; and

generating, by a memory trace combiner stored on the computer readable storage medium executed by the programmable processor, a memory trace of the program code executable based on the record of static memory address information and the record of the dynamic address information.

5. A system comprising:

a programmable processor coupled to a computer readable storage medium configured to execute:

an instrumentation module configured to:

analyze a program code for a target processor to detect a loop nest of the program code having regular memory access and a location of the detected loop nest in the program code, wherein a loop nest is associated with an instruction address and includes a loop iteration variable indicating a number of iterations of the loop nest;

determine a memory access pattern of the loop nest based on memory access instructions in the loop nest;

provide, based on the analyzing, a record of static memory address information associated with the loop nest by:

generating a memory access pattern function describing the memory address pattern of the loop nest by a start address of the memory access pattern of the loop nest and the loop iteration variable,

generating memory access pattern parameters representing the instruction address and a size of a memory access based on the loop iteration variable, and

generating the static memory address information from the memory access pattern function and the memory access pattern parameters; and

instrument the program code to provide an instrumented code for the target processor comprising the program code supplemented with an instrumentation instruction at an entry point of the loop nest, the instrumentation instruction to be executed only once per instantiation of the loop nest and to output an information message during runtime by the target processor, that comprises a dynamic memory address information field formatted to store a dynamic memory address information associated with the loop nest, that indicates a runtime value of a start address of the memory access pattern of the loop nest and the memory access pattern of the loop nest, wherein the information message includes a runtime value of the instruction address;

a compiler configured to compile the instrumented code to obtain an instrumented executable program for the target processor;

a loader to load the instrumented executable program for the target processor;

an information collector to:

receive the record of static memory address information from the instrumentation module;

receive, when the instrumented executable program is executed by the target processor, the information message from the target processor;

extract the dynamic address information from the information message; and

collect the dynamic address information to obtain a record of the dynamic address information; and

a memory trace combiner to generate a memory trace for the loop nest based on combining the record of static memory address information with the record of the dynamic address information.

6. The system according to claim 5 , wherein

the dynamic memory address information field is further formatted to store in respective information fields a runtime value of an instruction address related to the loop nest, the runtime value of the start address of the memory access pattern of the loop nest, and a runtime value of an iteration count of loop variables of the loop nest.

7. A method comprising:

analyzing, by an instrumentation module stored on a computer readable storage medium to be executed by a programmable processor coupled to the computer readable storage medium, a program code for a target processor to detect a loop nest of the program having regular memory access and a location of the detected loop nest in the program code, wherein a loop nest is associated with an instruction address and includes a loop iteration variable indicating a number of iterations of the loop nest;

determining, by the instrumentation module, a memory access pattern of the loop nest based on memory access instructions in the loop nest;

providing, based on the analyzing, a record of static memory address information associated with the loop nest, wherein providing the record of the static memory address information associated with the loop nest includes:

generating a memory access pattern function describing the memory address pattern of the loop nest by a start address of the memory access pattern of the loop nest and the loop iteration variable,

generating memory access pattern parameters representing the instruction address and a size of a memory access based on the loop iteration variable, and

generating the static memory address information from the memory access pattern function and the memory access pattern parameters;

instrumenting, by the instrumentation module, the program code to provide an instrumented code for the target processor comprising the program code supplemented with an instrumentation instruction inserted at an exit point of the detected loop nest based on the location of the detected loop nest, the instrumentation instruction to be executed only once per instantiation of the loop nest and to output an information message during runtime by the target processor that comprises a dynamic memory address information field formatted to store a dynamic memory address information associated with the loop nest that indicates a runtime value of a start address of the memory access pattern of the loop nest based on the loop nest and the memory access pattern of the loop nest, wherein the information message is based on the record of the static memory address information; and

storing and compiling, by the target processor, the instrumented code for the target processor for executing the instrumented code to generate a memory trace for the loop nest.

8. The method according to claim 7 , wherein

the dynamic memory address information field is further formatted to store in respective information fields a runtime value of an instruction address related to the loop nest, the runtime value of the start address of the memory access pattern of the loop nest, and a runtime value of an iteration count of loop variables of the loop nest.

Assignments (24)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0535 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0444 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037358/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035034/0019 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0923 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 27, 2014
From: BADEA, DRAGOS; MIHAILA, ANDREI
To: FREESCALE SEMICONDUCTOR INC
Reel/Frame 034035/0602 →
Continuity (1)
Related Publication 20150082284A1 · Mar 19, 2015