IP Library › Granted Patent US 9,899,294
Granted Patent B2
US 9,899,294 · App. 14/910,280 · Granted Feb 20, 2018

Thermal interface material layer and package-on-package device including the same

Inventors: Min-Ok Na (Bucheon-si, KR); Jongkook Kim (Hwaseong-si, KR); Hyo-Chang Ryu (Cheonan-si, KR); Jin-woo Park (Seoul, KR); BongJin Son (Asan-si, KR); Jangwoo Lee (Seoul, KR)
Assignee: Samsung Electronics co., Ltd.
H01L23/373H01L21/563H01L23/367H01L25/065H01L25/105H01L25/50H01L23/49827H01L23/50H01L24/16H01L24/32H01L24/48H01L24/73H01L24/92H01L25/0657H01L2224/0401H01L2224/04042H01L2224/16225H01L2224/32145H01L2224/32225H01L2224/48091H01L2224/48227H01L2224/73204H01L2224/73253H01L2224/73265H01L2224/92225H01L2225/0651H01L2225/06568H01L2225/107H01L2225/1023H01L2225/1058H01L2225/1094H01L2924/00014H01L2924/15311H01L2924/15331H01L2924/181H01L2924/18161
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Quick Facts
Patent No.
US 9,899,294
App. No.
14/910,280
Granted
Feb 20, 2018
Kind
B2
Abstract

Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.

Claims (21)

1. A thermal interface material layer interposed between a lower semiconductor package and an upper semiconductor package, the thermal interface material layer having a modulus of elasticity of 500 kPa or less,

wherein the thermal interface material layer includes a resin layer and filler particles distributed in the resin layer, and

the resin layer has a modulus of elasticity of 500 kPA or less.

2. The thermal interface material layer of claim 1 , wherein the thermal interface material layer has Mohs hardness that is lower than 7.

3. The thermal interface material layer of claim 1 , wherein the thermal interface material layer has thermal conductivity of 1 W/mK or higher.

4. The thermal interface material layer of claim 1 , wherein the resin layer is formed of a silicon-based compound or a rubber-based compound.

5. The thermal interface material layer of claim 1 , wherein the filler particles have Mohs hardness that is lower than 7.

6. The thermal interface material layer of claim 5 , wherein the filler particles are configured to exhibit an insulation property.

7. The thermal interface material layer of claim 6 , wherein the filler particles are at least one of boron nitride particles and zinc oxide particles.

8. The thermal interface material layer of claim 6 , wherein at least one of the filler particles comprises a metal particle coated with an insulating layer, and the metal particle has Mohs hardness that is lower than 7.

9. The thermal interface material layer of claim 1 , wherein a content of the filler particles in the thermal interface material layer ranges from 60 wt % to 95 wt %.

10. The thermal interface material layer of claim 1 , wherein the thermal interface material layer has a Mohs hardness that is lower than 7.

11. The thermal interface material layer of claim 10 , wherein the thermal interface material layer has modulus of elasticity of 500 kPa or less.

12. The thermal interface material layer of claim 10 , wherein the thermal interface material layer has thermal conductivity of 1 W/mK or higher.

13. The thermal interface material layer of claim 10 , wherein

the filler particles have Mohs hardness that is lower than 7.

14. The thermal interface material layer of claim 13 , wherein the filler particles are configured to exhibit an insulation property.

15. The thermal interface material layer of claim 13 , wherein the filler particles are at least one of boron nitride particles and zinc oxide particles.

16. The thermal interface material layer of claim 13 , wherein at least one of the filler particles comprises a metal particle coated with an insulating layer, and the metal particle has Mohs hardness that is lower than 7.

17. The thermal interface material layer of claim 1 , wherein the resin layer is formed of a silicon-based compound or a rubber-based compound.

18. The thermal interface material layer of claim 13 , wherein a content of the filler particles in the thermal interface material layer ranges from 60 wt % to 95 wt %.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE TWO INVENTORS NAMES OMITTED PREVIOUSLY RECORDED AT REEL: 037732 FRAME: 0662. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 24, 2016
From: NA, MIN-OK; KIM, JONGKOOK; RYU, HYO-CHANG; PARK, JIN-WOO; SON, BONGJIN; LEE, JANGWOO
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 037899/0577 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2016
From: NA, MIN-OK; KIM, JONGKOOK; RYU, HYO-CHANG; PARK, JIN-WOO
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 037732/0662 →
Continuity (1)
Related Publication 20160190035A1 · Jun 30, 2016