Alternative threshold voltage scheme via direct metal gate patterning for high performance CMOS FinFETs

1. A method of forming a semiconductor structure comprising:

forming at least one first semiconductor fin located in a first device region of a substrate, at least one second semiconductor fin located in a second device region of the substrate, at least one third semiconductor fin located in a third device region of the substrate, and at least one fourth semiconductor fin located in a fourth device region of the substrate;

forming a gate cavity exposing a channel portion of each of the at least one first semiconductor fin, the at least one second semiconductor fin, the at least one third semiconductor fin, and the at least one fourth semiconductor fin, wherein the gate cavity is laterally surrounded by an interlevel dielectric (ILD) layer;

forming a gate dielectric layer on sidewalls and bottom surfaces of the gate cavity and a topmost surface of the ILD layer;

forming a gate dielectric cap layer over the gate dielectric layer;

removing a portion of the gate dielectric cap layer from the second, the third and the fourth device regions;

forming a p-type work function metal layer over a portion of the gate dielectric layer exposed in the second, the third and the fourth device regions and a remaining portion of the gate dielectric cap layer located in the first device region;

removing a portion of the p-type work function metal layer from the third and fourth device regions;

forming a barrier layer over a portion of the gate dielectric layer exposed in the third and the fourth device regions and a remaining portion of the p-type work function metal layer located in the first and second device regions;

forming an n-type work function metal layer over the barrier layer, wherein the n-type work function metal layer completely fills a first portion of the gate cavity located in the first device region;

forming a metal cap layer over the n-type work function metal layer;

removing a portion of the metal cap layer from the first, the second and the fourth device regions; and

forming a gate electrode layer over portions of the n-type work function metal layer exposed in the first, the second and the fourth device regions and a remaining portion of the metal cap layer located in the third device region, wherein the gate electrode layer completely fills a remaining portion of the gate cavity.

2. The method of claim 1 , further comprising annealing the gate dielectric cap layer prior to the patterning the gate dielectric cap layer.

3. The method of claim 2 , wherein the annealing the gate dielectric cap layer comprises:

forming a sacrificial cap layer on the gate dielectric cap layer;

annealing the gate dielectric cap layer at an elevated temperature; and

removing the sacrificial cap layer.

4. The method of claim 3 , wherein the sacrificial cap layer comprises amorphous silicon or polysilicon.

5. The method of claim 3 , further comprising forming a sacrificial hardmask layer on the annealed gate dielectric cap layer.

6. The method of claim 5 , further comprising forming an etch stop layer on the n-type work function metal layer prior to the forming the metal cap layer.

7. The method of claim 6 , further comprising forming an adhesion layer over the portions of the n-type work function metal layer exposed in the first, the second and the fourth device regions and the remaining portion of the metal cap layer located in the third device region prior to the forming the gate electrode layer.

8. The method of claim 1 , further comprising removing portions of the gate electrode layer, the remaining portion of the metal cap layer, the n-type work function metal layer, the barrier layer, the remaining portion of the p-type work function metal layer, the remaining portion of the gate dielectric cap layer and the gate dielectric layer that are located above the topmost surface of the ILD layer.

9. The method of claim 1 , wherein the forming the gate cavity comprises:

forming a sacrificial gate stack over the channel portion of the at least one first semiconductor fin, the at least one second semiconductor fin, the at least one third semiconductor fin, and the at least one fourth semiconductor fin;

forming a gate spacer on each sidewall of the sacrificial gate stack;

forming the ILD layer laterally surrounding the gate spacer; and

removing the sacrificial gate stack.

10. The method of claim 1 , wherein the forming the at least one first semiconductor fin, the at least one second semiconductor fin, the at least one third semiconductor fin, and the at least one fourth semiconductor fin comprises:

providing a bulk semiconductor substrate; and

patterning an upper portion of the bulk semiconductor substrate.

11. The method of claim 1 , wherein the forming the at least one first semiconductor fin, the at least one second semiconductor fin, the at least one third semiconductor fin, and the at least one fourth semiconductor fin comprises:

providing a semiconductor-on-insulator substrate comprising a top semiconductor layer; and

patterning the top semiconductor layer of the semiconductor-on-insulator substrate.

12. The method of claim 2 , wherein the annealing is carried out in an ambient atmosphere containing nitrogen at a temperature from 600° C. to 1100° C.

13. The method of claim 1 , wherein the forming the p-type workfunction metal layer comprises a conformal deposition process.

14. The method of claim 1 , wherein the p-type workfunction metal layer comprises TiN.

15. The method of claim 1 , wherein the forming the p-type workfunction metal layer comprises depositing a p-type workfunction metal at a temperature from 420° C. to 500° C.

16. The method of claim 1 , wherein the n-type work function metal layer is selected from the group consisting of TiAlC, TaAlC, TiAl, Ti, and Al.

17. The method of claim 1 , wherein the substrate is an insulator layer or a semiconductor material.

18. The method of claim 1 , further comprising forming, prior to forming the gate cavity, first source/drain regions in each of the first and second device regions, and second source/drain regions in each of the third and fourth device regions.

19. The method of claim 18 , wherein each of the first source/drain regions and each of the second source/drain regions are raised source/drain regions.

20. The method of claim 18 , wherein the first source/drain regions in the first device region are formed into a portion of the at least one first semiconductor fin, the first source/drain regions in the second device region are formed into a portion of the at least one second semiconductor fin, the second source/drain regions in the third device region are formed into a portion of the at least one third semiconductor fin, and the second source/drain regions in the second device region are formed into a portion of the at least one fourth semiconductor fin.