Replacement gate structures for transistor devices

1. A transistor device, comprising:

a gate structure positioned above a semiconductor substrate, said gate structure comprising:

a gate insulation layer comprising a high-k dielectric material having a dielectric constant of approximately 10 or greater;

a conductive gate electrode material positioned above said gate insulation layer; and

at least one work function adjusting metal layer positioned between said gate insulation layer and said conductive gate electrode material; and

spaced-apart sidewall spacers positioned above said substrate and adjacent sidewalls of said gate structure, an internal sidewall surface of each of said spaced-apart sidewall spacers comprising an upper sidewall surface portion and a lower sidewall surface portion positioned between said upper sidewall surface portion and a surface of said substrate, wherein a first lateral width between first upper ends of said upper sidewall surface portions is greater than a second lateral width between second upper ends of said lower sidewall surface portions, wherein said gate insulation layer covers a portion of said substrate and an entirety of said lower sidewall surface portions of said sidewall spacers but does not extend between or cover any of said upper sidewall surface portions of said sidewall spacers, and wherein said at least one work function adjusting metal layer covers an entirety of said gate insulation layer but does not extend between or cover any of said upper sidewall surface portions of said sidewall spacers.

2. The transistor device of claim 1 , wherein said transistor device is an NMOS transistor device.

3. The transistor device of claim 1 , wherein said transistor device is a PMOS transistor device.

4. The transistor device of claim 1 , wherein said internal sidewall surfaces of said spaced-apart sidewall spacers each have a stepped cross-sectional configuration and define a first space therebetween having said first lateral width and a second space therebetween having said second lateral width.

5. The transistor device of claim 4 , wherein a lower portion of said gate structure fills said second space and has said second lateral width and an upper portion of said gate structure fills said first space and has said first lateral width.

6. The transistor device of claim 1 , wherein said upper sidewall surface portion of said internal sidewall surface of each of said spaced-apart sidewall spacers is an outwardly tapered surface extending substantially continuously from a first lower end proximate said second upper end of said lower sidewall surface portion to said first upper end proximate an upper surface of said gate structure.

7. The transistor device of claim 6 , wherein a space defined between said lower sidewall surface portions of said spaced-apart sidewall spacers has a substantially constant width extending from second lower ends of said lower sidewall surface portions proximate said surface of said substrate to said second upper ends of said lower sidewall surface portions proximate said first lower ends of said upper sidewall surface portions.

8. The transistor device of claim 6 , wherein a lower portion of said gate structure extends between said lower sidewall surface portions of said spaced-apart sidewall spacers and has said substantially constant width extending from said second lower ends of said lower sidewall surface portions proximate said surface of said substrate to said second upper ends of said lower sidewall surface portions proximate said first lower ends of said upper sidewall surface portions.

9. The transistor device of claim 6 , wherein a lateral width between said outwardly tapered upper sidewall surface portions of said spaced-apart sidewall spacers increases from said second lateral width at said first lower ends of said upper sidewall surface portions proximate said second upper ends of said lower sidewall surface portions to said first lateral width at said first upper ends of said upper sidewall surface portions proximate said upper surface of said gate structure.

10. A transistor device, comprising:

a gate structure positioned above a semiconductor substrate, said gate structure comprising:

a gate insulation layer comprising a high-k dielectric material having a dielectric constant of approximately 10 or greater;

a conductive gate electrode material positioned above said gate insulation layer; and

at least one work function adjusting metal layer positioned between said gate insulation layer and said conductive gate electrode material; and

spaced-apart sidewall spacers positioned above said substrate and adjacent sidewalls of said gate structure, wherein an internal sidewall surface of each of said spaced-apart sidewall spacers has a stepped cross-sectional configuration comprising an upper sidewall surface portion and a lower sidewall surface portion positioned between said upper sidewall surface portion and an upper surface of said substrate, said upper sidewall surface portions defining a first space therebetween having a substantially constant first lateral width extending from lower ends of said upper sidewall surface portions located proximate respective upper ends of said lower sidewall surface portion to upper ends of said upper sidewall surface portions located proximate an upper surface of said gate structure, and said lower sidewall surface portions defining a second space therebetween having a substantially constant second lateral width extending from lower ends of said lower sidewall surface portions located proximate said upper surface of said substrate to said upper ends of said lower sidewall surface portions located proximate said respective lower ends of said upper sidewall surface portions, wherein said first lateral width is greater than said second lateral width, wherein said gate insulation layer covers a portion of said substrate and an entirety of said lower sidewall surface portions of said sidewall spacers but does not extend between or cover any of said upper sidewall surface portions of said sidewall spacers, and wherein said at least one work function adjusting metal layer covers an entirety of said gate insulation layer but does not extend between or cover any of said upper sidewall surface portions of said sidewall spacers.

11. The transistor device of claim 10 , wherein said at least one work function adjusting metal layer is a first work function adjusting metal layer, said gate structure further comprising at least a second work function adjusting metal layer positioned between said first work function adjusting metal layer and said conductive gate electrode material, wherein said at least said second work function adjusting metal layer covers an entirety of said first work function adjusting metal layer and extends between and covers at least some of said upper sidewall surface portions of said sidewall spacers.

12. An integrated circuit product, comprising:

a first transistor, comprising:

a first gate structure comprising a first work function adjusting metal layer positioned above a first gate insulation layer; and

a first pair of sidewall spacers positioned adjacent opposite sidewalls of said first gate structure, each of said first pair of sidewall spacers having internal sidewall surfaces comprising a first untrimmed lower surface portion and a first trimmed upper surface portion located above said first untrimmed lower surface portion, wherein a lateral width between upper ends of said first trimmed upper surface portions is greater than a lateral width between upper ends of said first untrimmed lower surface portions, wherein said first gate insulation layer covers an entirety of said first untrimmed lower surface portions of said first pair of sidewall spacers but does not extend between or cover any of said first trimmed upper surface portions of said first pair of sidewall spacers; and

a second transistor, comprising:

a second gate structure comprising a second work function adjusting metal layer positioned above a second gate insulation layer; and

a second pair of sidewall spacers positioned adjacent opposite sidewalls of said second gate structure, each of said second pair of sidewall spacers having internal sidewall surfaces comprising a second untrimmed lower surface portion and a second trimmed upper surface portion located above said second untrimmed lower surface portion, wherein a lateral width between upper ends of said second trimmed upper surface portions is greater than a lateral width between upper ends of said second untrimmed lower surface portions, wherein said second gate insulation layer covers an entirety of said second untrimmed lower surface portions of said second pair of sidewall spacers but does not extend between or cover any of said second trimmed upper surface portions of said second pair of sidewall spacers, and wherein said second work function adjusting metal layer covers an entirety of said second gate insulation layer but does not extend between or cover any of said second trimmed upper surface portions of said second pair of sidewall spacers.

13. The integrated circuit product of claim 12 , wherein said first transistor is an NMOS transistor, said first work function adjusting metal layer is an NMOS work function adjusting metal layer, said second transistor is a PMOS transistor, and said second work function adjusting metal layer is a PMOS work function adjusting metal layer, wherein a first portion of said NMOS work function adjusting metal layer is laterally positioned between said first untrimmed lower surface portions of said first pair of sidewall spacers and a second portion of said NMOS work function adjusting metal layer is laterally positioned between said first trimmed upper surface portions of said first pair of sidewall spacers, and wherein said PMOS work function adjusting metal layer is laterally positioned between said second untrimmed lower surface portions of said second pair of sidewall spacers.

14. The integrated circuit product of claim 13 , wherein an entirety of said PMOS work function adjusting metal layer is laterally positioned between said second untrimmed lower surface portions of said second pair of sidewall spacers and does not extend between said second trimmed upper surface portions of said second pair of sidewall spacers.

15. The integrated circuit product of claim 13 , wherein said gate structure of said PMOS transistor further comprises a second NMOS work function adjusting metal layer positioned above said PMOS work function adjusting metal layer, a first portion of said second NMOS work function adjusting metal layer being laterally positioned between said second untrimmed lower surface portions of said second pair of sidewall spacers and a second portion of said second NMOS work function adjusting metal layer being laterally positioned between said second trimmed upper surface portions of said second pair of sidewall spacers.

16. The integrated circuit product of claim 12 , wherein said internal sidewall surfaces of said respective first and second pairs of sidewall spacers each define a stepped configuration when viewed in cross-section.

17. The integrated circuit product of claim 12 , wherein said first and second trimmed upper surface portions of said respective first and second pairs of sidewall spacers each define a tapered configuration when viewed in cross-section.