IP Library Granted Patent US 10,008,466
Granted Patent B2
US 10,008,466 · App. 15/729,127 · Granted Jun 26, 2018

Semiconductor device and manufacturing method thereof

Inventor: Hiroyuki Utsunomiya (Ibaraki, JP)
Assignee: RENESAS ELECTRONICS CORPORATION
H01L24/13H01L24/11H01L24/03H01L24/05H01L2224/0345H01L2224/03462H01L2224/03831H01L2224/03912H01L2224/0401H01L2224/05572H01L2224/05647H01L2224/10145H01L2224/1147H01L2224/11462H01L2224/11849H01L2224/11903H01L2224/131H01L2224/13005H01L2224/13014H01L2224/13017H01L2224/13018H01L2224/13083H01L2224/13147H01L2224/13155H01L2224/16237H01L2224/81191H01L2224/81193H01L2224/81424H01L2224/81444H01L2224/81447H01L2224/81455H01L2224/81469H01L2924/206
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,008,466
App. No.
15/729,127
Granted
Jun 26, 2018
Kind
B2
Abstract

A flip-chip mounting technique with high reliability is provided in flip-chip mounting using a Cu pillar. In a semiconductor device to be coupled to a mounting board via a Cu pillar, the Cu pillar is caused to have a laminated structure including a pillar layer, a barrier layer, and a bump in this order from below, and the bump is formed to be smaller than the barrier layer.

Claims (45)

1. A manufacturing method of a semiconductor device, comprising the steps of:

(a) applying a resist film having an opening over a terminal pad formed over a semiconductor substrate;

(b) forming a pillar layer, a barrier layer, and a bump in the opening in this order from below;

(c) removing the resist film;

(d) etching outer peripheries of the bump; and

(e) reflowing the bump by a heat treatment such that a width of the bump is smaller than that of the barrier layer in a cross section of the semiconductor device.

2. The manufacturing method of a semiconductor device according to claim 1 ,

wherein, in the step (d), the etching is performed by using dilute hydrofluoric acid.

3. The manufacturing method of a semiconductor device according to claim 1 ,

wherein, in the step (b), the pillar layer, the barrier layer, and the bump are formed by electrolytic plating.

4. The manufacturing method of a semiconductor device according to claim 1 ,

wherein, in the step (c), the resist film is removed by ashing.

5. The manufacturing method of a semiconductor device according to claim 1 ,

wherein, in the step (d), the outer peripheries of the bump are wet etched.

6. The manufacturing method of a semiconductor device according to claim 1 ,

wherein the pillar layer is a Cu film,

wherein the barrier layer is an Ni film, and

wherein the bump is an SnAg film.

7. A manufacturing method of a semiconductor device, comprising the steps of:

(a) applying a first resist film over a terminal pad formed over a main surface of a semiconductor substrate;

(b) forming a first opening in the first resist film for exposing the terminal pad in the bottom thereof;

(c) forming a pillar layer and a barrier layer in this order from below;

(d) removing the first resist film;

(e) applying a second resist film over the terminal pad, the pillar layer, and the barrier layer;

(f) forming a second opening in the second resist film for exposing the barrier layer in the bottom thereof;

(g) forming a bump in the second opening; and

(h) removing the second resist film.

8. The manufacturing method of a semiconductor device according to claim 7 ,

wherein a diameter of the second opening is smaller than that of the first opening.

9. The manufacturing method of a semiconductor device according to claim 7 ,

wherein, in the step (b), the first opening is formed by photolithography.

10. The manufacturing method of a semiconductor device according to claim 7 ,

wherein, in the step (c), the pillar layer and the barrier layer are formed by electrolytic plating.

11. The manufacturing method of a semiconductor device according to claim 7 ,

wherein, in the step (d), the first resist film is removed by ashing.

12. The manufacturing method of a semiconductor device according to claim 7 ,

wherein, in the step (f), the second opening is formed by photolithography.

13. The manufacturing method of a semiconductor device according to claim 7 ,

wherein, in the step (g), the bump is formed by electrolytic plating.

14. The manufacturing method of a semiconductor device according to claim 7 ,

wherein, in the step (h), the second resist film is removed by ashing.

15. The manufacturing method of a semiconductor device according to claim 7 ,

wherein the pillar layer is a Cu film,

wherein the barrier layer is an Ni film, and

wherein the bump is an SnAg film.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 10, 2017
From: UTSUNOMIYA, HIROYUKI
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 043827/0774 →
Priority Claims (1)
JP 2015-093059 · Apr 30, 2015 · national
Continuity (2)
Division 15098138 · Apr 13, 2016
Related Publication 20180047691A1 · Feb 15, 2018