Phase change memory cell with constriction structure
Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.
1. A device comprising:
a first electrode and a second electrode;
a memory element directly contacting the first and second electrodes, the memory element including a programmable portion having a material configured to change between multiple phases to store information based on a resistance state of an amorphous region of the programmable portion, wherein the programmable portion is isolated from the first electrode by a first portion of the memory element, and wherein the programmable portion is isolated from the second electrode by a second portion of the memory element, and the resistance state is based on a size of the amorphous region; and wherein
the first portion of the memory element includes a tapered part and a larger part, the larger part is between the tapered part and the first electrode, and the programmable portion includes at least a part of the tapered part;
the second portion of the memory element includes a first part and a second part, the first part contacts the second electrode, the second part is between the first part and the tapered part, wherein the first part and the second part have a same width, and the width is measured in a direction perpendicular to a direction from the first electrode to the second electrode; and
the programmable portion having the material configured to change between multiple phases includes a portion of the tapper part and a portion of the second part.
2. The device of claim 1 , wherein the memory element is configured to cause the material of the programmable portion to have a first phase of the multiple phases and to cause a material of each of the first and second portions to have a second phase of the multiple phases.
3. The device of claim 2 , wherein the material of programmable portion and the material at each of the first and second portion include chalcogenide material.
4. The device of claim 1 , wherein a material of each of the first and second portion has a crystalline phase.
5. The device of claim 1 , wherein the programmable portion is configured to store information representing multiple bits.
6. The device of claim 1 , wherein the memory element is configured to cause the size of the amorphous region to have a first thickness corresponding to a first value of the resistance state, and a second thickness corresponding to a second value of the resistance state.
7. The device of claim 6 , wherein the memory element is configured to cause the size of the amorphous region to have a third thickness corresponding to a third value of the resistance state.
8. The device of claim 1 , wherein the memory element is configured to cause the size of the amorphous region to have a first thickness corresponding to a first value of information stored in the memory element, and a second thickness corresponding to a second value of information stored in the memory element.
9. The device of claim 8 , wherein the memory element is configured to cause the size of the amorphous region to have a third thickness corresponding to a third first value of information stored in the memory element.
10. The device of claim 1 , wherein the first portion includes a first cross-section area to pass a first current, the second portion includes a second cross-section area to pass a second current, and the programmable portion includes a third cross-section to pass a third current, and the third cross-section area is smaller than each of the first and second cross-section areas.
11. The device of claim 1 , wherein the programmable portion includes chalcogenide material.
12. The device of claim 1 , wherein the material includes a compound of germanium, antimony, and tellurium.
13. The device of claim 1 , further comprising an access component coupled to the memory element.
14. The device of claim 13 , wherein one of the access component and the memory element is coupled to a wordline, and the other one of the access component and the memory element is coupled to a bit line.
15. The device of claim 13 , wherein the access component includes a field-effect transistor coupled to a wordline, and the memory element is coupled to a bit line.
16. The device of claim 13 , wherein the access component includes a bipolar junction transistor coupled to a wordline, and the memory element is coupled to a bit line.
17. The device of claim 13 , wherein the access component includes a diode coupled to a wordline, and the memory element is coupled to a bit line.