Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device
Sacrificial semiconductor material portions are connected by a sacrificial semiconductor line extending along a different horizontal direction and protruding into an underlying source conductive layer. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through the sacrificial semiconductor material portions. A backside trench can be formed through the vertically alternating stack employing the sacrificial semiconductor line as an etch stop structure. Source strap material portions providing lateral electrical contact to semiconductor channels of the memory stack structures can be formed by replacement of sacrificial semiconductor material portions and the sacrificial semiconductor line with source strap material portions. Structural-reinforcement portions may be employed to provide structural stability during the replacement process.
1. A three-dimensional memory device comprising:
a source semiconductor layer having a thickness modulation and located over a substrate and including a recess region;
source strap material portions located over the source semiconductor layer, and the recess region is filled by a same semiconductor material as the source strap material portions;
a vertically alternating stack of electrically conductive layers and insulating layers located over the source strap material portions;
an array of memory stack structures that extend through the vertically alternating stack and into an upper portion of the source semiconductor layer, each memory stack structure including a semiconductor channel and a memory film laterally surrounding the semiconductor channel and including an opening through which a respective one of the source strap material portions contacts the semiconductor channel;
an insulating wall structure vertically extending through the vertical alternating stack and laterally extending along a same direction as the recess region and protruding downward into portions of the source strap material portions; and
a cap semiconductor layer overlying the source strap material portions and underlying the vertically alternating stack, contacting top surfaces of the source strap material portions, and not contacting, and laterally spaced from, sidewalls of the insulating wall structure by a bottommost insulating layer within the vertically alternating stack.
2. The three-dimensional memory device of claim 1 , wherein a topmost surface of the source semiconductor layer contacts bottom surfaces of the source strap material portions outside the recess region.
3. The three-dimensional memory device of claim 1 , wherein:
sidewalls of the source semiconductor layer contact sidewalls of the source strap material portions at a periphery of the recess region; and
a recessed top surface of the source semiconductor layer contacts a downward-protruding portion of the source strap material portions at a bottom of the recess region.
4. The three-dimensional memory device of claim 1 , wherein the source strap material portions comprise a doped semiconductor material having a doping of a same conductivity type as the source semiconductor layer.
5. The three-dimensional memory device of claim 1 , wherein the insulating wall structure contacts sidewalls of the insulating layers, sidewalls of the electrically conductive layers, sidewalls of the source strap material portions, and recessed top surfaces of the source strap material portions.
6. The three-dimensional memory device of claim 1 , further comprising a cap semiconductor layer overlying the source strap material portions and underlying the vertically alternating stack and contacting sidewalls of the insulating wall structure and top surfaces of the source strap material portions.
7. The three-dimensional memory device of claim 1 , further comprising:
dielectric material portions located at a same level as the source strap material portions; and
at least one patterned dielectric liner that overlies the dielectric material portions and underlying the cap semiconductor layer.
8. The three-dimensional memory device of claim 1 , wherein;
the array of memory stack structures protrudes downward into the source semiconductor layer; and
each memory film comprises, from outside to inside, a blocking dielectric, a charge storage layer, and a tunneling dielectric layer.
9. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
the substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;
the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.
10. A three-dimensional memory device comprising:
a source semiconductor layer having a thickness modulation and located over a substrate and including a recess region;
source strap material portions located over the source semiconductor layer, and the recess region is filled by a same semiconductor material as the source strap material portions;
a vertically alternating stack of electrically conductive layers and insulating layers located over the source strap material portions;
an array of memory stack structures that extend through the vertically alternating stack and into an upper portion of the source semiconductor layer, each memory stack structure including a semiconductor channel and a memory film laterally surrounding the semiconductor channel and including an opening through which a respective one of the source strap material portions contacts the semiconductor channel;
an insulating wall structure vertically extending through the vertical alternating stack and laterally extending along a same direction as the recess region and protruding downward into portions of the source strap material portions; and
a cap semiconductor layer overlying the source strap material portions and underlying the vertically alternating stack and contacting top surfaces of the source strap material portions;
dielectric material portions located at a same level as the source strap material portions; and
at least one patterned dielectric liner that overlies the dielectric material portions and underlying the cap semiconductor layer.
11. The three-dimensional memory device of claim 10 , wherein a topmost surface of the source semiconductor layer contacts bottom surfaces of the source strap material portions outside the recess region.
12. The three-dimensional memory device of claim 10 , wherein:
sidewalls of the source semiconductor layer contact sidewalls of the source strap material portions at a periphery of the recess region; and
a recessed top surface of the source semiconductor layer contacts a downward-protruding portion of the source strap material portions at a bottom of the recess region.
13. The three-dimensional memory device of claim 10 , wherein the source strap material portions comprise a doped semiconductor material having a doping of a same conductivity type as the source semiconductor layer.
14. The three-dimensional memory device of claim 10 , wherein the insulating wall structure contacts sidewalls of the insulating layers, sidewalls of the electrically conductive layers, sidewalls of the source strap material portions, and recessed top surfaces of the source strap material portions.
15. The three-dimensional memory device of claim 10 , further comprising a cap semiconductor layer overlying the source strap material portions and underlying the vertically alternating stack and contacting sidewalls of the insulating wall structure and top surfaces of the source strap material portions.
16. The three-dimensional memory device of claim 10 , wherein;
the array of memory stack structures protrudes downward into the source semiconductor layer; and
each memory film comprises, from outside to inside, a blocking dielectric, a charge storage layer, and a tunneling dielectric layer.
17. The three-dimensional memory device of claim 10 , wherein:
the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
the substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;
the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.