Three-dimensional semiconductor devices

1. A three-dimensional semiconductor device, comprising:

a lower structure including three-dimensionally arranged lower memory devices;

an upper structure on the lower structure, the upper structure including conductive patterns;

a semiconductor pattern electrically connected to the lower structure through the upper structure; and

a pad pattern interposed between the lower memory devices and the semiconductor pattern to electrically connect the semiconductor pattern to the lower memory devices, wherein the pad pattern has a recessed region, and the semiconductor pattern has a lower portion provided in the recessed region of the pad pattern.

2. The device as claimed in claim 1 , wherein a bottom surface of the semiconductor pattern is at a vertical level lower than an uppermost surface of the pad pattern.

3. The device as claimed in claim 1 , wherein the pad pattern has a recessed upper surface that is in direct contact with a bottom surface of the semiconductor pattern.

4. The device as claimed in claim 1 , further comprising

an insulating spacer between the semiconductor pattern and the upper structure,

wherein a bottom surface of the insulating spacer being positioned at a vertical level substantially equivalent to or higher than an uppermost surface of the pad pattern.

5. The device as claimed in claim 1 , wherein the lower structure includes a selection transistor, wherein the selection transistor is interposed between a semiconductor layer and the upper structure, the selection transistor including a selection semiconductor pattern directly connected to the pad pattern.

6. The device as claimed in claim 1 , wherein the upper structure further includes:

interlayer dielectric patterns sequentially stacked on the lower structure and interposed between the conductive patterns; and

an intermediate layer interposed between the conductive patterns and the semiconductor pattern; and

the device further includes an insulating spacer being interposed between the interlayer dielectric pattern and the semiconductor pattern.

7. The device as claimed in claim 6 , wherein a lowermost layer of the interlayer dielectric patterns is interposed between a lowermost layer of the conductive patterns and the pad pattern, the lowermost layer of the interlayer dielectric patterns being in direct contact with the pad pattern.

8. A three-dimensional semiconductor device, comprising:

a first layered electrode structure including a plurality of first electrodes stacked in a first direction away from a substrate;

a second layered electrode structure on the first layered electrode structure, the second layered electrode structure including a plurality of second electrodes stacked in the first direction away from the substrate;

a first vertical channel extending through the first layered electrode structure;

a second vertical channel extending through the second layered electrode structure; and

a pad pattern electrically connecting the first vertical channel and the second vertical channel, wherein a bottom surface of the second vertical channel is at a vertical level lower than an uppermost surface of the pad pattern.

9. The device as claimed in claim 8 , further comprising an upper insulating spacer between the second vertical channel and the second electrodes.

10. The device as claimed in claim 9 , wherein the bottom surface of the upper insulating spacer being positioned at a vertical level substantially equivalent to or higher than an uppermost surface of the pad pattern.

11. The device as claimed in claim 9 , wherein a bottom surface of the upper insulating spacer is positioned between a bottom surface of a lowermost layer of the first electrodes and an uppermost surface of the pad pattern.

12. The device as claimed in claim 9 , wherein the upper insulating spacer includes at least one of a tunnel insulating layer, a blocking insulating layer, and a charge storing layer.

13. The device as claimed in claim 9 , wherein a distance between the bottom surface of the upper insulating spacer and the uppermost surface of the pad pattern is less than a thickness of one of the second electrodes.

14. The device as claimed in claim 8 , wherein the pad pattern has a recessed upper surface that is in direct contact with the bottom surface of the second vertical channel.

15. The device as claimed in claim 8 , wherein the pad pattern includes a semiconductor material having a different conductivity type from the first and second vertical channels.

16. The device as claimed in claim 8 , wherein the second layered electrode structure further includes interlayer dielectric patterns sequentially stacked on the second layered electrode structure and interposed between the second electrodes, and wherein a lowermost layer of the interlayer dielectric patterns is interposed between a lowermost layer of the second electrodes and the pad pattern.

17. The device as claimed in claim 8 , further comprising an intermediate layer interposed between the second electrodes and the second vertical channel, wherein the intermediate layer extends horizontally from a region between the second electrodes and the second vertical channel to cover top and bottom surfaces of the second electrodes.

18. The device as claimed in claim 8 , wherein a bottom surface of the first vertical channel is at a vertical level lower than an uppermost surface of the substrate.

19. The device as claimed in claim 8 , further comprising a lower insulating spacer between the first vertical channel and the first electrodes.

20. The device as claimed in claim 19 , wherein a bottom surface of the lower insulating spacer is positioned between a bottom surface of a lowermost layer of the first electrodes and an lowermost surface of the substrate.