Elevationally-extending string of memory cells and methods of forming an elevationally-extending string of memory cells
A method that is part of a method of forming an elevationally-extending string of memory cells comprises forming an intervening structure that is elevationally between upper and lower stacks that respectively comprise alternating tiers comprising different composition materials. The intervening structure is formed to comprise an elevationally-extending-dopant-diffusion barrier and laterally-central material that is laterally inward of the dopant-diffusion barrier and has dopant therein. Some of the dopant is thermally diffused from the laterally-central material into upper-stack-channel material. The dopant-diffusion barrier during the thermally diffusing is used to cause more thermal diffusion of said dopant into the upper-stack-channel material than diffusion of said dopant, if any, into lower-stack-channel material. Other embodiments, including structure independent of method, are disclosed.
1. A method of forming an elevationally-extending string of memory cells, comprising:
forming a lower stack comprising first-alternating tiers comprising different composition first- and second-lower-stack materials, insulator material above the lower stack, and a lower opening extending through the insulator material and through the first-alternating tiers;
forming lower-stack-channel material in the lower opening;
forming laterally-central material in the lower opening, the laterally-central material comprising an uppermost region having dopant therein and a lowermost dopant-diffusion-barrier region;
forming conductive material in the lower opening electrically coupled with the lower-stack-channel material;
providing lower control-gate material laterally outward of the lower-stack-channel material; and
providing lower insulative-charge-passage material, lower charge-storage material, and a lower charge-blocking region laterally between the lower control-gate material and the lower-stack-channel material;
forming an upper stack comprising second-alternating tiers comprising different composition first and second-upper-stack materials elevationally over the lower stack, the laterally-central material in the lower opening, and the conductive material in the lower opening; the upper stack having an upper opening extending elevationally through the second-alternating tiers and to at least one of the laterally-central material and the conductive material in the lower opening;
forming upper-stack-channel material in the upper opening that is electrically coupled with the lower-stack-channel material through the conductive material in the lower opening;
providing upper control-gate material laterally outward of the respective upper stack-channel material; and
providing upper insulative-charge-passage material, upper charge-storage material, and an upper charge-blocking region laterally between the upper control-gate material and the upper stack-channel material.
2. The method of claim 1 comprising forming the conductive material to comprise conductively-doped semiconductive material.
3. The method of claim 1 comprising forming the conductive material to comprise metal material.
4. The method of claim 1 comprising forming the upper-stack-channel material directly against the laterally-central material.
5. The method of claim 1 comprising forming the upper-stack-channel material directly against the conductive material.
6. A method of forming an elevationally-extending string of memory cells, comprising:
forming a lower stack comprising a plurality of vertically-alternating tiers comprising control-gate material vertically alternating with insulating material;
forming a lower-stack-channel pillar extending through the plurality of the vertically-alternating tiers of the lower stack;
forming a conductive interconnect over the lower-stack-channel pillar, the conductive interconnect comprising side material laterally outward of and extending elevationally along a laterally-central material, and comprising a dopant-barrier material, the lower-stack-channel pillar being directly against the side material;
forming an upper stack elevationally over the lower stack, the upper stack comprising a plurality of vertically-alternating tiers comprising control-gate material vertically alternating with insulating material;
forming an upper-stack-channel pillar extending through the plurality of the vertically-alternating tiers in the upper stack; and
forming insulative-charge-passage material, charge-storage material, and a charge-blocking region of individual of the memory cells being laterally between upper-stack-channel pillar and the control-gate material, the conductive interconnect being elevationally between and electrically coupling the upper-stack-channel pillar and lower-stack-channel pillar together.
7. The method of claim 6 wherein the lower-stack-channel pillar is directly against an elevationally-innermost surface of the side material.
8. The method of claim 6 wherein the side material comprises metal material.
9. The method of claim 6 wherein the side material comprises conductively-doped semiconductive material.
10. The method of claim 6 wherein the side material comprises an elevationally-extending cylinder.
11. The method of claim 10 wherein the side material comprises metal material.
12. The method of claim 10 wherein the side material comprises conductively-doped semiconductive material.