Semiconductor device and method of manufacturing the same
A semiconductor device includes a first stacked structure having first conductive layers and first insulating layers formed alternately with each other, first semiconductor patterns passing through the first stacked structure, a coupling pattern coupled to the first semiconductor patterns, and a slit passing through the first stacked structure and the coupling pattern.
1 . A semiconductor device, comprising:
a first stacked structure including a first semiconductor pattern, first conductive layers and first insulating layers, the first conductive layers formed alternately with the first insulating layers along a sidewall of the first semiconductor pattern;
a second stacked structure located under the first stacked structure, and including a second semiconductor pattern, second conductive layers and second insulating layers, the second conductive layers formed alternately with the second insulating layers along a sidewall of the second semiconductor pattern;
a slit passing through the first stacked structure and the second stacked structure; and
a third insulating layer interposed between the first stacked structure and the second stacked structure and including a coupling pattern,
wherein a lower surface of the third insulating layer contacts an uppermost second insulating layer and an upper surface of the third insulating layer contacts a lowermost first insulating layer,
wherein the coupling pattern couples the first semiconductor pattern to the second semiconductor pattern,
wherein the coupling pattern has a first sidewall adjacent to the third insulating layer and a second sidewall adjacent to the slit, and
wherein
the third insulating layer covers the first sidewall and is absent from the second sidewall, and
the second sidewall of the coupling pattern adjacent the slit aligns with an edge of the first insulating layers adjacent the slit.
2 . The semiconductor device of claim 1 , further comprising a peripheral circuit located under the second stacked structure.
3 . The semiconductor device of claim 1 , wherein the first conductive layers and the second conductive layers include polysilicon.
4 . The semiconductor device of claim 1 , further comprising:
a first data storage layer surrounding the sidewall of the first semiconductor pattern, and
a second data storage layer surrounding the sidewall of the second semiconductor pattern.
5 . The semiconductor device of claim 4 ,
wherein the first data storage layer includes polysilicon interposed between the first semiconductor pattern and each of the first conductive layers, and
wherein the second data storage layer includes polysilicon interposed between the second semiconductor pattern and each of the second conductive layers.
6 . A semiconductor device, comprising:
a first stacked structure including a first semiconductor pattern, first conductive layers and first insulating layers, the first conductive layers formed alternately with the first insulating layers along a sidewall of the first semiconductor pattern;
a second stacked structure located under the first stacked structure, and including a second semiconductor pattern, second conductive layers and second insulating layers, the second conductive layers formed alternately with the second insulating layers along a sidewall of the second semiconductor pattern;
a slit passing through the first stacked structure and the second stacked structure;
a third insulating layer interposed between the first stacked structure and the second stacked structure and including a coupling pattern, wherein a lower surface of the third insulating layer contacts an uppermost second insulating layer and an upper surface of the third insulating layer contacts a lowermost first insulating layer; and
a multilayer dielectric layer surrounding the sidewall of the first semiconductor pattern and the sidewall of the second semiconductor pattern,
wherein the coupling pattern has a first sidewall adjacent to the third insulating layer and a second sidewall adjacent to the slit, and
wherein
the third insulating layer covers the first sidewall and is absent from the second sidewall, and
the second sidewall of the coupling pattern adjacent the slit aligns with an edge of the first insulating layers adjacent the slit.
7 . The semiconductor device of claim 6 , wherein the multilayer dielectric layer is divided into a first multilayer dielectric layer surrounding the sidewall of the first semiconductor pattern and a second multilayer dielectric layer surrounding the sidewall of the second semiconductor pattern.
8 . The semiconductor device of claim 6 , wherein the coupling pattern includes an uneven portion surrounding the first semiconductor pattern at different heights.
9 . The semiconductor device of claim 6 , further comprising a peripheral circuit located under the second stacked structure.
10 . The semiconductor device of claim 6 , wherein the multilayer dielectric layer extends to partially or entirely cover a sidewall of the coupling pattern.
11 . A semiconductor device, comprising:
a first stacked structure including a first semiconductor pattern, first conductive layers and first insulating layers, the first conductive layers formed alternately with the first insulating layers along a sidewall of the first semiconductor pattern;
a second stacked structure located under the first stacked structure, and including a second semiconductor pattern, second conductive layers and second insulating layers, the second conductive layers formed alternately with the second insulating layers along a sidewall of the second semiconductor pattern;
a slit passing through the first stacked structure and the second stacked structure;
a third insulating layer interposed between the first stacked structure and the second stacked structure, wherein a lower surface of the third insulating layer contacts an uppermost second insulating layer and an upper surface of the third insulating layer contacts a lowermost first insulating layer;
a coupling pattern formed in the third insulating layer and the uppermost second insulating layer; and
a multilayer dielectric layer surrounding the sidewall of the first semiconductor pattern and the sidewall of the second semiconductor pattern,
wherein the coupling pattern has a first sidewall adjacent to the third insulating layer and a second sidewall adjacent to the slit, and
wherein
the third insulating layer covers the first sidewall and is absent from the second sidewall, and
the second sidewall of the coupling pattern adjacent the slit aligns with an edge of the first insulating layers adjacent the slit.
12 . The semiconductor device of claim 11 , wherein the multilayer dielectric layer is divided into a first multilayer dielectric layer surrounding the sidewall of the first semiconductor pattern and a second multilayer dielectric layer surrounding the sidewall of the second semiconductor pattern.
13 . The semiconductor device of claim 11 , wherein the coupling pattern includes an uneven portion surrounding the first semiconductor pattern at different heights.
14 . The semiconductor device of claim 11 , further comprising a peripheral circuit located under the second stacked structure.
15 . The semiconductor device of claim 11 , wherein the multilayer dielectric layer extends to partially or entirely cover a sidewall of the coupling pattern.
16 . A semiconductor device, comprising:
a first stacked structure including a first semiconductor pattern, first conductive layers and first insulating layers, the first conductive layers formed alternately with the first insulating layers along a sidewall of the first semiconductor pattern;
a second stacked structure located under the first stacked structure, and including a second semiconductor pattern, second conductive layers and second insulating layers, the second conductive layers formed alternately with the second insulating layers along a sidewall of the second semiconductor pattern;
a slit passing through the first stacked structure and the second stacked structure;
a third insulating layer interposed between the first stacked structure and the second stacked structure, wherein a lower surface of the third insulating layer contacts an uppermost second insulating layer and an upper surface of the third insulating layer contacts a lowermost first insulating layer; and
a coupling pattern including a horizontal portion and a vertical portion protruding from the horizontal portion,
wherein the third insulating layer includes the horizontal portion of the coupling pattern,
wherein the horizontal portion of the coupling pattern has a first sidewall adjacent to the third insulating layer and a second sidewall adjacent to the silt slit, and
wherein
the third insulating layer covers the first sidewall and is absent from the second sidewall, and
the second sidewall of the coupling pattern adjacent the slit aligns with an edge of the first insulating layers adjacent the slit.
17 . The semiconductor device of claim 16 , wherein the horizontal portion of the coupling pattern is coupled to the first semiconductor pattern.
18 . The semiconductor device of claim 16 , wherein the vertical portion of the coupling pattern is coupled to the second semiconductor pattern.
19 . The semiconductor device of claim 16 , wherein the vertical portion of the coupling pattern is in the uppermost second insulating layer.
20 . The semiconductor device of claim 19 , further comprising:
a multilayer dielectric layer surrounding the sidewall of the first semiconductor pattern, the sidewall of the second semiconductor pattern and the vertical portion of the coupling pattern.
21 . The semiconductor device of claim 16 , wherein the coupling pattern includes an uneven portion surrounding the first semiconductor pattern at different heights.
22 . The semiconductor device of claim 16 , further comprising a peripheral circuit located under the second stacked structure.