Dual-port semiconductor memory and first in first out (FIFO) memory having electrically floating body transistor

1. A semiconductor memory array comprising:

a plurality of multi-port semiconductor memory cells arranged in a matrix of rows and columns, wherein each said multi-port semiconductor memory cell comprises:

a plurality of gates;

a common body region of a first conductivity type configured to store a charge that is indicative of a memory state of said memory cell;

a plurality of conductive regions of a second conductivity type,

wherein adjacent ones of each of said plurality of gates are separated by a respective one of the plurality of conductive regions, and wherein the common body region extends continuously beneath at least one of the plurality of conductive regions;

a region of a second conductivity type electrically connected to a back bias terminal,

wherein applying a voltage to said back bias terminal results in at least two stable common body region charge levels; and

wherein said back bias terminal is commonly connected to at least two of said multi-port semiconductor memory cells.

2. The semiconductor memory array of claim 1 , wherein each of the plurality of gates is configured to provide at least one of read access from and write access to the multi-port semiconductor memory cell independently of all other of the plurality of gates.

3. The semiconductor memory array of claim 1 , wherein each said multi-port semiconductor memory cell includes a total number of ports, said plurality of conductive regions comprises a total number of conductive regions, and said plurality of gates comprises a total number of gates, wherein the total number of ports is equal to the total number of gates, and further wherein the total number of conductive regions is one more than the total number of gates.

4. The semiconductor memory array of claim 1 , wherein the plurality of conductive regions is in electrical communication with the common body region, and further wherein each of the plurality of conductive regions is spaced apart from all others of the plurality of conductive regions.

5. The semiconductor memory array of claim 1 , wherein at least a portion of the common body region separates each of the plurality of conductive regions from all others of the plurality of conductive regions.

6. The semiconductor memory array of claim 1 , wherein the plurality of conductive regions and the common body region form a plurality of diodes.

7. The semiconductor memory array of claim 1 , wherein the multi-port semiconductor memory cell includes a fin structure, and further wherein the fin structure includes the common body region.

8. The semiconductor memory array of claim 7 , wherein the fin structure is an elongate fin structure that includes a longitudinal axis, and further wherein the plurality of gates is spaced apart along the longitudinal axis.

9. The semiconductor memory array of claim 7 , wherein the fin structure further includes the plurality of conductive regions.

10. The semiconductor memory array of claim 1 , wherein said voltage applied to said back bias terminal is a constant positive voltage bias.

11. The semiconductor memory array of claim 1 , wherein said voltage applied to said back bias terminal is a periodic pulse of positive voltage.

12. A semiconductor memory array comprising:

a plurality of multi-port semiconductor memory cells arranged in a matrix of rows and columns, wherein each said multi-port semiconductor memory cell comprises:

a plurality of transistors, each of the plurality of transistors comprising:

a common body region configured to store a charge that is indicative of the state of said multi-port semiconductor memory cell; and

a plurality of gates,

wherein said common body region is shared among the plurality of transistors;

a layer beneath said common body region wherein said common body region is positioned between said plurality of gates and said layer; and

a back bias terminal connected to said layer and configured to perform at least one of injecting a charge into and extracting the charge out of the common body region to maintain said memory state of the multi-port semiconductor memory cell resulting in at least two stable common body region charge levels,

wherein said back bias terminal is commonly connected to at least two of said multi-port semiconductor memory cells.

13. The semiconductor memory array of claim 12 , wherein each of the plurality of gates is configured to provide at least one of read access from and write access to the multi-port semiconductor memory cell independently of all other of the plurality of gates.

14. The semiconductor memory array of claim 12 , wherein each said multi-port semiconductor memory cell includes a total number of ports and wherein said plurality of gates consists of a total number of gates, wherein the total number of ports is equal to the total number of gates.

15. The semiconductor memory array of claim 14 , wherein each said multi-port semiconductor memory cell further comprises a total number of conductive regions, wherein said total number of conductive regions is one more than said total number of gates.

16. The semiconductor memory array of claim 12 , wherein the multi-port semiconductor memory cell includes a fin structure, and further wherein the fin structure includes the common body region.

17. The semiconductor memory array of claim 16 , wherein the fin structure is an elongate fin structure that includes a longitudinal axis, and further wherein the plurality of gates is spaced apart along the longitudinal axis.

18. The semiconductor memory array of claim 16 , wherein the fin structure further includes a plurality of conductive regions.

19. The semiconductor memory array of claim 12 , wherein a voltage bias applied to said back bias terminal is a constant positive voltage bias.

20. The semiconductor memory array of claim 12 , wherein a voltage bias applied to said back bias terminal is a periodic pulse of positive voltage.