Diode-triggered schottky silicon-controlled rectifier for Fin-FET electrostatic discharge control

1. A fin-type field effect transistor (FinFET) structure comprising:

a substrate;

a silicon-controlled rectifier (SCR) over the substrate, the SCR including:

a p-well region and an adjacent n-well region over the substrate; and

a negatively charged fin over the p-well region;

a Schottky diode electrically coupled with the SCR, the Schottky diode for controlling electrostatic discharge (ESD) across the negatively charged fin and the n-well region;

a first additional n-well region adjacent the p-well region;

a first additional p-well region adjacent the first additional n-well region;

a second additional n-well region adjacent the first additional p-well region;

a second additional p-well region adjacent the second additional n-well region;

a third additional n-well region adjacent the second additional p-well region;

three diodes coupled in series with the Schottky diode,

wherein each of the three diodes is located within the first additional n-well region, the second additional n-well region and the third additional n-well region, respectively; and

additional sets of negatively charged fins and positively charged fins over each of the first additional n-well region, the second additional n-well region, and the third additional n-well region.

2. The FinFET structure of claim 1 , wherein the Schottky diode includes a gate in the n-well region.

3. The FinFET structure of claim 1 , wherein the SCR includes a P-N-P-N switch.

4. The FinFET structure of claim 3 , wherein the substrate is p-type doped.

5. The FinFET structure of claim 4 , wherein the P-N-P-N switch includes the p-type substrate, the n-well region, the p-well region and the negatively charged fin.

6. The FinFET structure of claim 1 , further comprising a positively charged fin over the p-well region and an additional negatively charged fin over the n-well region.

7. The FinFET structure of claim 1 , wherein each of the three diodes includes an anode in the additional positively charged fin over the first, second and third additional n-well regions, and a cathode in each of the first, second and third additional n-well regions.

8. A fin-type field effect transistor (FinFET) structure comprising:

a p-type substrate;

a silicon-controlled rectifier (SCR) over the p-type substrate, the SCR including:

a p-well region and an adjacent n-well region over the substrate; and

a negatively charged fin over the p-well region, wherein the negatively charged fin includes a metal; and

a Schottky diode electrically coupled with the SCR, the Schottky diode including a gate in the n-well region, the Schottky diode positioned to mitigate electrostatic discharge (ESD) across the negatively charged fin and the n-well region in response to application of a forward voltage across the gate, wherein the negatively charged fin acts as an anode region of the Schottky diode.

9. The FinFET structure of claim 8 , wherein the SCR includes a P-N-P-N switch.

10. The FinFET structure of claim 9 , wherein the P-N-P-N switch includes the p-type substrate, the n-well region, the p-well region and the negatively charged fin.

11. The FinFET structure of claim 8 , further comprising a positively charged fin over the p-well region and an additional negatively charged fin over the n-well region.

12. The FinFET structure of claim 8 , further comprising:

a first additional n-well region adjacent the p-well region;

a first additional p-well region adjacent the first additional n-well region;

a second additional n-well region adjacent the first additional p-well region;

a second additional p-well region adjacent the second additional n-well region; and

a third additional n-well region adjacent the second additional p-well region.

13. The FinFET structure of claim 12 , further comprising three diodes coupled in series with the Schottky diode.

14. The FinFET structure of claim 13 , wherein each of the three diodes is located within the first additional n-well region, the second additional n-well region and the third additional n-well region, respectively.

15. The FinFET structure of claim 14 , further comprising additional sets of negatively charged fins and positively charged fins over each of the first additional n-well region, the second additional n-well region, and the third additional n-well region.

16. The FinFET structure of claim 15 , wherein each of the three diodes includes an additional anode in the additional positively charged fin over the first, second and third additional n-well regions, and a cathode in each of the first, second and third additional n-well regions.