Core independent peripheral based ultrasonic ranging peripheral
A ranging function is implemented using a collection of core independent peripherals (CIPs) in a microcontroller without software overhead to the central processor during operation thereof. A pulse width modulation (PWM) peripheral generates a high frequency drive signal, a counter to set the duration of the PWM drive signal (pulse), and a second timer coupled to a comparator to measure the time it takes to receive back a reflection of the ranging signal from an object. The ranging peripheral starts ranging with ultrasonic pulses, and when corresponding reflected ultrasonic pulse are receives an interrupt signal is provided when the ranging measurement is complete. Time dependent sensitivity and/or gain adjustments are contemplated. The ultrasonic ranging peripheral uses on chip resources for most of its functions and therefore requires very few external components. It's set and forget nature may be based on CIP based timers, signal generators and configurable logic cells.
1. An ultrasonic ranging measurement device, comprising:
a microcontroller comprising
a central processor and memory,
a plurality of core independent peripherals (CIPs) including at least:
a capture compare pulse width modulation (CCP),
a comparator (CMP),
a first and second configurable logic cells (CLC) each at least configurable as a RS flip-flop,
a data signal modulator (DSM),
a fixed voltage reference (FVR),
an operational amplifier (OPA),
a pulse width modulation generator (PWM), and
a first, second and third timer (TMR) each coupled with a timer counter register;
an ultrasonic transmitting transducer coupled to the DSM; and
an ultrasonic receiving transducer coupled to the OPA;
wherein the selected CIPs are configured to generate signals to be transmitted as ultrasonic pulses from the ultrasonic transmitting transducer, receive signals representing reflected ultrasonic pulses from an object with the ultrasonic receiving transducer, detect the reflected ultrasonic pulse signals, and store times between the transmitted ultrasonic pulse signals and the corresponding reflected ultrasonic pulse signals that are received and detected.
2. The ultrasonic ranging measurement device according to claim 1 , wherein the CIPs generate the ultrasonic pulse signals, receive and detect the reflected ultrasonic pulse signals and store the times between the transmitted ultrasonic pulse signals and the corresponding reflected ultrasonic pulse signals without intervention from the central processor of the microcontroller.
3. The ultrasonic ranging measurement device according to claim 1 , wherein logic functions of the CLC are selected from the group consisting of a flip-flop, a NOR gate, an NAND gate, a XNOR gate, an AND gate, an OR gate, and a XOR gate.
4. The ultrasonic ranging measurement device according to claim 3 , wherein the CLC comprises at least two of the logic functions.
5. The ultrasonic ranging measurement device according to claim 1 , wherein:
an output from the DSM is coupled to the ultrasonic transmitting transducer;
the PWM is coupled to a first input of the DSM;
wherein the first CLC configured as a RS flip-flop has an output coupled to a second input of the DSM; and
wherein the first TMR has an input coupled to the output of the DSM, and an output coupled to a reset input of the first CLC;
wherein a start signal is coupled to a set input of the first CLC, whereby an ultrasonic pulse is generated each time the start signal is asserted and the ultrasonic pulse has a pulse duration determined by the first TMR.
6. The ultrasonic ranging measurement device according to claim 5 , further comprising:
a peak voltage detector coupled to an output of the OPA;
wherein a first input of the CMP is coupled to an output of the peak voltage detector, and a second input of the CMP is coupled to the FVR, wherein when a voltage from the peak voltage detector is greater than a reference voltage from the FVR an output of the CMP changes from a first logic level to a second logic level; and
wherein inputs of the CCP are coupled to the second TMR, wherein the CCP stores a time count value from the second TMR when the CMP output changes from the first logic level to the second logic level;
wherein the second TMR resets back to a zero time count value after the start signal is asserted.
7. The ultrasonic ranging measurement device according to claim 6 , wherein
the third TMR is configured as a one-shot timer and coupled between the output of the first CLC and a set input of the second CLC; and
the second CLC has a reset input coupled to the start signal and an output coupled to a start input of the second TMR;
wherein the second CLC starts the second TMR counting after the third TMR one-shot timer has timed out.
8. The ultrasonic ranging measurement device according to claim 6 , wherein
a done signal is generated from the output of the CMP when the reflected ultrasonic pulse is detected; and
a fault signal is generated by the second TMR when no reflected ultrasonic pulse is detected.
9. The ultrasonic ranging measurement device according to claim 6 , wherein the input to the OPA comprises differential inputs coupled to the ultrasonic receiving transducer having differential outputs.
10. The ultrasonic ranging measurement device according to claim 5 , further comprising:
a programmable ramp generator (PRG) within the microcontroller, and
a peak voltage detector coupled to an output of the OPA;
wherein the CMP has a first input coupled to an output of the peak voltage detector, and a second input coupled to the PRG, wherein when a voltage from the peak voltage detector is greater than a voltage from the PRG an output of the CMP changes from a first logic level to a second logic level; and
wherein the CCP has inputs coupled to the second TMR, wherein the CCP stores a time count value from the second TMR when the CMP output changes from the first logic level to the second logic level;
wherein the second TMR resets back to a zero time count value after the start signal is asserted.
11. The ultrasonic ranging measurement device according to claim 10 , wherein the voltage from the PRG decreases over time, thereby causing the CMP to change from the first logic level to the second logic level at a lower voltage from the peak voltage detector over time.
12. The ultrasonic ranging measurement device according to claim 11 , wherein an input to the PRG is configured to be coupled to the FVR.
13. The ultrasonic ranging measurement device according to claim 12 , further comprising within the microcontroller a buffer OPA coupled between the PRG and the second input of the CMP.
14. The ultrasonic ranging measurement device according to claim 7 , further comprising:
a programmable ramp generator (PRG) within the microcontroller,
wherein the OPA is a gain controllable OPA, and wherein the PRG is coupled to and configured to control the gain of the gain controllable OPA, wherein the PRG is further configured to cause the gain of the gain controllable OPA to increase over time, thereby increasing receive sensitivity for the reflected ultrasonic pulse.
15. The ultrasonic ranging measurement device according to claim 14 , wherein the PRG starts increasing the receive sensitivity of the OPA once the second TMR starts counting.
16. The ultrasonic ranging measurement device according to claim 1 , wherein the ultrasonic pulses are at about 40 kHz.
17. The ultrasonic ranging measurement device according to claim 1 , wherein the microcontroller is in a single integrated circuit package.
18. A method for providing an ultrasonic ranging measurement device, comprising the steps of:
providing a microcontroller having a central processor and memory, and a plurality of core independent peripherals (CIPs);
selecting from the plurality of CIPs at least the following:
a capture compare pulse width modulation (CCP),
a comparator (CMP),
a first and second configurable logic cell (CLC) each at least configurable as a RS flip-flop,
a data signal modulator (DSM),
a fixed voltage reference (FVR),
an operational amplifier (OPA),
a pulse width modulation generator (PWM), and
a first, second and third timer (TMR) each coupled with a timer counter register;
coupling an ultrasonic transmitting transducer to the DSM; and
coupling an ultrasonic receiving transducer to the OPA;
generating signals from the DM to be transmitted as ultrasonic pulses from the ultrasonic transmitting transducer;
receiving reflected ultrasonic pulses from an object with the ultrasonic receiving transducer and generating receive signals to the OPA; and
storing times between the transmitted ultrasonic pulse signals and the corresponding reflected ultrasonic pulse signals that are received and detected.
19. The method according to claim 18 , wherein the steps of:
transmitting the ultrasonic pulse signals;
receiving and detecting the reflected ultrasonic pulses; and
storing the times between the transmitted ultrasonic pulse signals and the corresponding reflected ultrasonic pulse signals are done without intervention from the central processor of the microcontroller.
20. The method according to claim 18 , further comprising:
configuring the microcontroller:
to couple an output from the DSM to the ultrasonic transmitting transducer;
to couple the PWM to a first input of the DSM;
to configure the first CLC as a RS flip-flop and to couple an output of the CLC to a second input of the DSM; and
to couple an input of the first TMR to the output of the DSM, and an output of the first TMR to a reset input of the first CLC; and
forwarding a start signal to a set input of the first CLC, whereby an ultrasonic pulse is generated each time the start signal is asserted and the ultrasonic pulse has a pulse duration determined by the first TMR.
21. The method according to claim 20 , further comprising:
providing a peak voltage detector coupled to an output of the OPA;
configuring the microcontroller to couple a first input of the CMP to an output of the peak voltage detector, and to couple a second input of the CMP to the FVR, wherein when a voltage from the peak voltage detector is greater than a reference voltage from the FVR an output of the CMP changes from a first logic level to a second logic level; and
to couple inputs of the CCP to the second TMR, wherein the CCP stores a time count value from the second TMR when the CMP output changes from the first logic level to the second logic level; and
resetting the second TMR back to a zero time count value after the start signal is asserted.
22. The method according to claim 21 , wherein
configuring the third TMR as a one-shot timer and coupling the third TMR between the output of the first CLC and a set input of the second CLC; and
coupling a reset input of the second CLC to the start signal and an output coupled to a start input of the second TMR; and
starting the second TMR counting by the CLC after the third TMR one-shot timer has timed out.
23. The method according to claim 21 , wherein
Generating a done signal by the output of the CMP when the reflected ultrasonic pulse is detected; and
generating a fault signal by the second TMR when no reflected ultrasonic pulse is detected.
24. The method according to claim 21 ,
providing a peak voltage detector coupled to an output of the OPA;
configuring the microcontroller:
to enable a programmable ramp generator (PRG) within the microcontroller;
to couple a first input of the CMP to an output of the peak voltage detector, and to couple a second input of the CMP to the PRG, wherein when a voltage from the peak voltage detector is greater than a voltage from the PRG an output of the CMP changes from a first logic level to a second logic level; and
to couple inputs of the CCP to the second TMR, wherein the CCP stores a time count value from the second TMR when the CMP output changes from the first logic level to the second logic level; and
resetting the second TMR back to a zero time count value after the start signal is asserted.
25. The method according to claim 24 , wherein the voltage from the PRG decreases over time, thereby causing the CMP to change from the first logic level to the second logic level at a lower voltage from the peak voltage detector over time.
26. The method according to claim 25 , further comprising the step of configuring the microcontroller to couple an input to the PRG with the FVR.
27. The method according to claim 26 , further comprising the step of configuring the microcontroller to couple a buffer OPA within the microcontroller between the PRG and the second input of the CMP.
28. The method according to claim 22 , further comprising the steps of:
configuring the microcontroller:
to enable a programmable ramp generator (PRG) within the microcontroller,
and to couple the PRG to the OPA and to control a gain of the OPA, wherein the PRG is further configured to cause the gain of the OPA to increase over time, thereby increasing receive sensitivity for the reflected ultrasonic pulse.
29. The method according to claim 28 , further comprising the step of controlling the PRG to start increasing the receive sensitivity of the OPA once the second TMR starts counting.