IP Library › Granted Patent US 10,128,151
Granted Patent B2
US 10,128,151 · App. 15/381,826 · Granted Nov 13, 2018

Devices and methods of cobalt fill metallization

Inventors: Vimal Kamineni (Mechanicville, NY); James Kelly (Schenectady, NY); Praneet Adusumilli (Albany, NY); Oscar Van Der Straten (Guilderland Center, NY); Balasubramanian Pranatharthiharan (Watervliet, NY)
Assignee: GLOBALFOUNDRIES Inc.
H01L21/76883H01L21/76882H01L23/53209
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Quick Facts
Patent No.
US 10,128,151
App. No.
15/381,826
Granted
Nov 13, 2018
Kind
B2
Abstract

Devices and methods of fabricating integrated circuit devices via cobalt fill metallization are provided. A method includes, for instance, providing an intermediate semiconductor device having at least one trench, forming at least one layer of semiconductor material on the device, depositing a first cobalt (Co) layer on the second layer, and performing an anneal reflow process on the device. Also provided are intermediate semiconductor devices. An intermediate semiconductor device includes, for instance, at least one trench formed within the device, the trench having a bottom portion and sidewalls, at least one layer of semiconductor material disposed on the device, a first cobalt (Co) layer disposed on the at least one layer of semiconductor material, wherein the at least one layer of semiconductor material includes at least a first semiconductor material and a second semiconductor material.

Claims (35)

1. A method comprising:

providing an intermediate semiconductor device having at least one trench, the at least one trench having substantially parallel sidewalls;

forming at least one layer of semiconductor material on the device;

depositing a first cobalt (Co) layer on the at least one layer of semiconductor material;

performing an anneal reflow process on the device, wherein the anneal reflow process causes the first Co layer to reflow to a bottom portion of the trench without filling the trench; and

performing at least one cycle comprising:

depositing a Co layer over the device; and

performing an anneal reflow process on the device.

2. The method of claim 1 , wherein the performing an anneal process comprises performing an argon anneal reflow process.

3. The method of claim 1 , wherein the forming at least one layer of semiconductor material comprises depositing a layer of first semiconductor material on a bottom surface of the at least one trench and on the upper surface of the device.

4. The method of claim 3 , wherein the forming at least one layer of semiconductor material further comprises depositing a layer of second semiconductor material layer on the layer of first semiconductor material and over the device.

5. The method of claim 1 , wherein the depositing a first Co layer comprises depositing a continuous layer.

6. The method of claim 1 , wherein the depositing a first Co layer comprises depositing a conformal layer.

7. The method of claim 1 , wherein the performing an anneal reflow process comprises performing an argon anneal reflow process.

8. The method of claim 1 further comprising:

filling the at least one trench with Co;

performing an anneal reflow process; and

planarizing the device.

9. The method of claim 8 , wherein the performing an anneal reflow process comprises performing a H 2 anneal reflow process.

10. The method of claim 1 further comprising:

performing oxidation of at least a portion of the first Co layer;

removing at least a portion of the oxidized Co from the first Co layer;

filling the at least one trench with Co; and

planarizing the device.

11. The method of claim 10 , wherein the removing at least a portion of the oxidized Co comprises removing at least a portion of the oxidized Co by an electrochemical bath.

12. An intermediate semiconductor device comprising:

at least one trench formed within the device, the at least one trench comprising a bottom surface and substantially parallel sidewalls;

at least one layer of semiconductor material disposed on the device; and

a first cobalt (Co) layer disposed on the at least one layer of semiconductor material, wherein the first Co layer disposed on the bottom portion of the trench is thicker than the first Co layer disposed on the sidewalls of the trench and the trench is not completely filled,

wherein the at least one layer of semiconductor material comprises at least a first semiconductor material and a second semiconductor material, wherein the second semiconductor material comprises one or more materials chosen from titanium nitride (TiN), tungsten carbide (WC), tungsten nitride (WN), tantalum nitride (TaN), and ruthenium (Ru).

13. The device of claim 12 , wherein the first semiconductor material comprises one or more materials chosen from titanium (Ti), nickel (Ni), nickel platinum (NiPt), and cobalt (Co).

14. The device of claim 13 , wherein the first semiconductor material is disposed on the bottom surface of the at least one trench and the top surface of the device.

15. The device of claim 12 , wherein the first Co layer is a continuous layer.

16. The device of claim 12 , wherein the first Co layer is a conformal layer.

17. The device of claim 12 further comprising a plurality of Co layers on the first Co layer.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2020
From: GLOBALFOUNDRIES INC.
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 054633/0001 →
SECURITY AGREEMENT Recorded Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 19, 2016
From: KAMINENI, VIMAL; KELLY, JAMES; ADUSUMILLI, PRANEET; VAN DER STRATEN, OSCAR; PRANATHARTHIHARAN, BALASUBRAMANIAN
To: GLOBALFOUNDRIES INC.
Reel/Frame 040662/0252 →
Continuity (1)
Related Publication 20180174965A1 · Jun 21, 2018