Wafer dicing using femtosecond-based laser and plasma etch
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.
1. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:
patterning a mask with a femtosecond-based laser scribing process to provide a laser-scribed mask, the mask formed above the semiconductor wafer, and to provide scribe lines in regions of the semiconductor wafer between the integrated circuits; each of the scribe lines having a widest width in the semiconductor wafer, the widest width in the semiconductor wafer the same as a width of the scribe lines in the mask at an interface of the mask and the semiconductor wafer; and
plasma etching trenches into the semiconductor wafer to singulate the integrated circuits, the trenches corresponding to the scribe lines and each having the widest width.
2. The method of claim 1 , wherein patterning the mask with the femtosecond-based laser scribing process comprises using a laser having a wavelength of approximately less than or equal to 540 nanometers with a laser pulse width of approximately less than or equal to 400 femtoseconds.
3. The method of claim 1 , wherein plasma etching the semiconductor wafer comprises using a high density plasma etching process.
4. The method of claim 1 , wherein the mask is selected from the group consisting of a photo-resist layer and an I-line patterning layer.
5. The method of claim 1 , wherein the plurality of integrated circuits is separated by streets having a width of approximately 10 microns or smaller as measured at a device layer/substrate interface.
6. The method of claim 1 , wherein the plurality of integrated circuits has a non-restricted layout.
7. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:
patterning a mask and a portion of the semiconductor wafer with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits, the mask formed above the semiconductor wafer, wherein each of the trenches has a widest width in the semiconductor wafer, the widest width in the semiconductor wafer the same as a width of laser scribe lines in the mask at an interface of the mask and the semiconductor wafer; and
plasma etching the semiconductor wafer through the trenches to form corresponding trench extensions and to singulate the integrated circuits, wherein each of the corresponding trench extensions has the widest width.
8. The method of claim 7 , wherein plasma etching the semiconductor wafer comprises using a high density plasma etching process.
9. The method of claim 7 , wherein the mask is selected from the group consisting of a photo-resist layer and an I-line patterning layer.
10. The method of claim 7 , wherein each of the plurality of integrated circuits is separated by streets having a width of approximately 10 microns or smaller as measured at a device layer/substrate interface.
11. The method of claim 7 , wherein the plurality of integrated circuits has a non-restricted layout.
12. The method of claim 7 , wherein patterning the mask and the portion of the semiconductor wafer with the laser scribing process comprises using a laser having a wavelength of approximately less than or equal to 540 nanometers with a laser pulse width of approximately less than or equal to 400 femtoseconds.
13. The method of claim 12 , wherein plasma etching the semiconductor wafer comprises using a high density plasma etching process.