Methods of forming a CT pillar between gate structures in a semiconductor

1. A method comprising:

providing a semiconductor structure having a substrate and a plurality of fins extending upwards from the substrate;

disposing a CT pillar layer over the semiconductor structure;

lithographically patterning a CT mask over the CT pillar layer;

anisotropically etching the CT mask to remove exposed portions of the CT pillar layer and to form a CT pillar between the fins;

disposing a dummy gate structure across the CT pillar; and

replacing the dummy gate structure with first and second metal gate structures that are electrically isolated from each other by the CT pillar.

2. The method of claim 1 comprising reducing an initial width of the CT pillar to a final width.

3. The method of claim 2 comprising reducing the initial width of the CT pillar by one of a trimming process and a UV light curing process.

4. The method of claim 2 comprising:

reducing the initial width of the CT pillar to an intermediate width by a trimming process; and

reducing the intermediate width of the CT pillar to the final width by a UV light curing process.

5. The method of claim 1 wherein disposing a dummy gate structure comprising:

disposing a dummy gate layer over the semiconductor structure;

disposing a hardmask stack over the dummy gate layer;

patterning and etching the hardmask stack to form a top portion of the dummy gate structure and to exposed the dummy gate layer in regions not covered by the patterned hardmask stack; and

anisotropically etching the exposed regions of the dummy gate layer to form the dummy gate structure.

6. The method of claim 5 comprising forming gate spacers on sidewalls of the dummy gate structure such that the gate spacers become a part of the dummy gate structure.

7. The method of claim 6 comprising anisotropically etching overextensions of the CT pillar, which extend beyond the boundaries of the dummy gate structure, to remove the overextensions and to self-align the CT pillar with the dummy gate structure.

8. The method of claim 7 comprising anisotropically etching down exposed portions of the fins that are not covered by the dummy gate structure.

9. The method of claim 8 comprising epitaxially growing source and drain regions over the etched down fins.

10. The method of claim 1 wherein replacing the dummy gate structure comprises:

providing the dummy gate structure with a hardmask stack disposed over a dummy gate layer and gate spacers disposed on sidewalls of the dummy gate layer;

disposing an oxide fill layer over the semiconductor structure;

planarizing the oxide fill layer down to expose a top surface of the hardmask stack; and

removing the hardmask stack and dummy gate layer to form a gate trench between the gate spacers.

11. The method of claim 10 comprising:

disposing a gate dielectric layer within the gate trench;

disposing a gate metal stack over the gate dielectric layer to fill the gate trench;

recessing the gate metal stack below a height of the CT pillar; and

disposing a self-aligned contact cap on the metal gate stack to form the first and second metal gate structures.

12. The method of claim 1 wherein replacing the dummy gate structure comprises:

providing the dummy gate structure with a hardmask stack disposed over a dummy gate layer and gate spacers disposed on sidewalls of the dummy gate layer;

removing the hardmask stack and dummy gate layer to form a gate trench between the gate spacers;

disposing a gate metal stack over the semiconductor structure to fill the gate trench; and

recessing the gate metal stack below a height of the CT pillar.

13. The method of claim 12 comprising disposing a self-aligned contact cap on the metal gate stack to form the first and second metal gate structures.

14. The method of claim 2 wherein the final width is 15 nanometers or less.

15. The method of claim 2 wherein the final width is 10 nanometers or less.