Granted Patent B2

US 12,363,977 · App. 17/463,019 · Granted Jul 15, 2025

Inventors: Julien Frougier (Albany, NY); Ruilong Xie (Niskayuna, NY); Kangguo Cheng (Schenectady, NY); Dimitri Houssameddine (Sunnyvale, CA)

Assignee: International Business Machines Corporation

H10D64/018H01L21/31144H01L21/76832H10D30/024H10D30/62H10D62/115H10D62/119H10D64/015H10D84/0158H10D84/038H10D84/834

Abstract

Claims (56)

1. An apparatus comprising:

a substrate;

a central vertical pillar of dielectric material protruding upward from the substrate;

a left plurality of semiconductor fins protruding horizontally from a left side of the central vertical pillar above the substrate;

a right plurality of semiconductor fins protruding horizontally from a right side of the central vertical pillar opposite the left plurality of semiconductor fins;

left and right hard masks touching the central vertical pillar above the left and right plurality of semiconductor fins;

spacers and patterning material covering a surface of the left and right hard mask, the surface being opposite the left and right pluralities of semiconductor fins, wherein the spacers are on inner and outer distal ends of the patterning material and the spacers on the inner distal ends of the patterning material touch the central vertical pillar; and

a bottom dielectric insulating layer protruding horizontally left and right of the central vertical pillar below the left and right pluralities of fins and adjacent to the substrate.

2. The apparatus of claim 1 , wherein the central vertical pillar protrudes into the substrate.

3. The apparatus of claim 2 , wherein the bottom dielectric insulating layer is of a same material as, and integral with, the central vertical pillar.

4. The apparatus of claim 2 , wherein trenches are indented into the substrate, further comprising:

a dielectric liner covering the bottoms of the trenches; and

a shallow trench insulation material filling the trenches above the dielectric liner.

5. The apparatus of claim 4 , wherein the bottom dielectric insulating layer is of a same material as, and integral with, the dielectric liner.

6. The apparatus of claim 4 , wherein the bottom dielectric insulating layer comprises a portion adjacent the central vertical pillar that is of a same material as, and integral with, the central vertical pillar, and a portion distal from the central vertical pillar that is of a same material as, and integral with, the dielectric liner.

7. A semiconductor structure comprising:

a substrate;

a central vertical pillar of dielectric material protruding upward from the substrate;

a left plurality of semiconductor fins of a first composition protruding horizontally from a left side of the central vertical pillar above the substrate;

a right plurality of semiconductor fins of the first composition protruding horizontally from a right side of the central vertical pillar opposite the left plurality of semiconductor fins;

a second composition of semiconductor material interleaved between the left and right pluralities of semiconductor fins of the first composition;

left and right semiconductor fins of a third composition protruding horizontally from left and right sides of the central vertical pillar between the substrate and the left and right pluralities of semiconductor fins of the first composition;

left and right hard masks touching the central vertical pillar above the left and right pluralities of semiconductor fins of the first composition;

spacers covering inner and outer distal portions of a surface of the left and right hard mask, the surface being opposite the left and right pluralities of semiconductor fins of the first composition, wherein the spacers covering the inner distal portion of the surface of the left and right hard mask touch the central vertical pillar; and

patterning material covering an inner portion of the surface of the left and right hard mask and filling an area between the spacers.

8. A method comprising:

forming on a substrate a stack of nanosheets covered by a hard mask, wherein the stack of nanosheets comprise:

a plurality of semiconductor layers of a first composition;

a plurality of semiconductor layers of a second composition interleaved between the semiconductor layers of the first composition; and

a semiconductor layer of a third composition between the substrate and the plurality of semiconductor layers of the first composition;

forming on a surface of the hard mask opposite the stack of nanosheets, a pair of left and right etch masks separated by a pillar gap;

narrowing the pillar gap by forming spacers on distal ends of the etch masks, wherein the spacers partially fill the pillar gap;

forming a pillar trench between left and right halves of the stack of nanosheets by etching the hard mask and the stack of nanosheet through the pillar gap; and

depositing a central vertical pillar of dielectric material in the pillar trench.

9. The method of claim 8 , wherein forming the pillar trench also includes etching the substrate through the pillar gap.

10. The method of claim 9 , wherein the central vertical pillar extends from within the substrate up to a top surface of the left and right etch masks.

11. The method of claim 8 , further comprising forming a vertical gap between the stack of nanosheets and the substrate by selectively etching the semiconductor layer of the third composition from left and right sides of the stack of nanosheets, wherein the central vertical pillar supports the stack of nanosheets above the substrate.

12. The method of claim 11 , further comprising filling the vertical gap between the stack of nanosheets and the substrate by depositing a dielectric liner over the stack of nanosheets and the substrate.

13. The method of claim 11 , wherein the vertical gap extends only partway from the left and right sides of the stack of nanosheets toward the central vertical pillar, and a part of the vertical gap remains filled by remnants of the semiconductor layer of the third composition.

14. The method of claim 13 , further comprising filling the vertical gap between the stack of nanosheets and the substrate and forming distal portions of a bottom dielectric insulator by depositing a dielectric liner over the stack of nanosheets and the substrate.

15. The method of claim 14 , wherein the central vertical pillar is a sacrificial pillar, further comprising:

restoring the pillar trench by selectively etching the sacrificial pillar;

forming a partial vertical gap between the stack of nanosheets and the substrate by selectively etching the remnants of the semiconductor layer of the third composition from the pillar trench, wherein the dielectric liner supports the stack of nanosheets above the substrate; and

forming a final vertical pillar and a central portion of the bottom dielectric insulator by depositing a dielectric material into the partial vertical gap and the pillar trench.

16. The method of claim 8 , wherein the central vertical pillar is a sacrificial pillar, further comprising:

depositing a dielectric liner over the substrate and the stack of nanosheets;

restoring the pillar trench by selectively etching the sacrificial pillar; and

forming a vertical gap between the stack of nanosheets and the substrate by selectively etching the semiconductor layer of the third composition from the pillar trench, wherein the dielectric liner supports the stack of nanosheets above the substrate.

17. The method of claim 13 , further comprising forming a final vertical pillar and a bottom dielectric insulator by depositing a dielectric material into the vertical gap and the pillar trench.

18. The method of claim 8 , further comprising:

etching the central vertical pillar partially into the pillar trench, but above an uppermost sheet of the stack of nanosheets.

19. The method of claim 18 , further comprising:

removing the left and right etch masks, the spacers, and the hard mask.

20. The method of claim 19 , further comprising:

forming a plurality of vertical gaps between the plurality of semiconductor layers of the first composition by selectively etching the plurality of semiconductor layers of the second composition; and

depositing a gate stack composed of at least one dielectric layer and one conductive layer into the plurality of vertical gaps.

Assignments (1)

Continuity (1)

References Cited (22)