Devices with chamfer-less vias multi-patterning and methods for forming chamfer-less vias
Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.
1. A method comprising:
obtaining an intermediate semiconductor device;
performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern;
depositing an etching stack over the intermediate semiconductor device, wherein the etch stack comprises:
a protective mask layer over the intermediate semiconductor device;
a via etch stop layer over the protective mask layer; and
a hardmask over the via etch stop layer;
performing at least one via patterning process to the intermediate semiconductor device, wherein performing at least one via patterning process comprises:
coating the hardmask with a first photoresist layer;
performing lithography to pattern at least one first via opening;
forming a first spacer within the at least one first via opening;
etching the at least one first via opening into the hardmask to form at least one first hardmask opening smaller than the at least one first via opening; and
removing the first photoresist layer; and
transferring the at least one first hardmask opening into a portion of the intermediate semiconductor device, wherein the at least one first hardmask opening is self-aligned with at least a portion of the trench pattern.
2. The method of claim 1 , wherein the intermediate semiconductor device comprises:
a substrate;
a first substrate etch stop layer on the substrate;
a second substrate etch stop layer on the first substrate etch stop layer;
a low k layer on the second substrate etch stop layer;
a first dielectric layer on the low k layer;
a hardmask layer on the first dielectric layer; and
a second dielectric layer on the hardmask layer.
3. The method of claim 2 , further comprising:
performing a punch through the via etch stop layer in the at least one first hardmask opening to expose a portion of the protective mask layer;
etching through the protective mask layer, the hardmask layer on the first dielectric layer, the first dielectric layer, the low k layer, and the second substrate etch stop layer; and
etching through the first substrate etch stop layer.
4. The method of claim 2 , wherein performing the trench etch into the portion of the intermediate semiconductor device comprises:
etching into the hardmask layer;
performing an etch to transfer the trench pattern into the first dielectric layer and remove the second dielectric layer; and
etching into the low k layer to form at least one trench pattern opening.
5. The method of claim 4 , further comprising:
depositing a barrier layer into the at least one trench pattern opening and the at least one first hardmask opening;
performing a metal deposition process for the at least one trench pattern opening and the at least one first hardmask opening; and
polishing the intermediate semiconductor device to form metal filled trenches and vias.
6. The method of claim 5 , wherein the metal filled trenches and vias comprises:
a top edge;
a bottom surface; and
walls extending up from the bottom surface to the top edge;
wherein the walls do not have chamfered top edges.
7. The method of claim 1 , wherein performing at least one via patterning process further comprises:
performing at least one second via patterning process.
8. The method of claim 7 , wherein performing at least one second via patterning process comprises:
coating intermediate semiconductor device with a second photoresist layer, wherein the second photoresist layer fills the at least one first hardmask opening;
performing lithography to pattern at least one second via opening;
forming a second spacer within the at least one second via opening;
etching the at least one second via opening into the hardmask to form at least one second hardmask opening smaller than the at least one second via opening; and
removing the second photoresist layer.
9. The method of claim 8 , wherein performing at least one via patterning process comprises:
performing at least one third via patterning process.
10. The method of claim 9 , wherein the performing at least one third via patterning process comprises:
coating intermediate semiconductor device with a third photoresist layer, wherein the third photoresist layer fills the at least one second hardmask opening;
performing lithography to pattern at least one third via opening;
forming a third spacer within the at least one third via opening;
etching the at least one third via opening into the hardmask to form at least one third hardmask opening smaller than the at least one third via opening; and
removing the third photoresist layer.