Method for manufacturing semiconductor device
To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.
1. A semiconductor device comprising:
a gate electrode including copper;
a first gate insulating layer over the gate electrode, the first gate insulating layer including silicon and nitrogen;
a second gate insulating layer over the first gate insulating layer, the second gate insulating layer including silicon and oxygen;
an oxide semiconductor layer over and in direct contact with the second gate insulating layer, the oxide semiconductor layer comprising indium and zinc;
an insulating layer over a channel formation region of the oxide semiconductor layer, the insulating layer including silicon and oxygen;
a first conductive layer over the oxide semiconductor layer, the first conductive layer including copper;
a second conductive layer over the oxide semiconductor layer, the second conductive layer including copper;
a third conductive layer between the oxide semiconductor layer and the first conductive layer; and
a fourth conductive layer between the oxide semiconductor layer and the second conductive layer,
wherein the oxide semiconductor layer includes a first region and a second region,
wherein the first region includes a first top surface of the oxide semiconductor layer and a first bottom surface of the oxide semiconductor layer, and is in direct contact with the insulating layer,
wherein the second region includes a second top surface of the oxide semiconductor layer and a second bottom surface of the oxide semiconductor layer,
wherein the first conductive layer overlaps the second region,
wherein a thickness of the second region is smaller than a thickness of the first region,
wherein a length of the third conductive layer in a channel length direction of the oxide semiconductor layer is larger than a length of the first conductive layer in the channel length direction of the oxide semiconductor layer, and
wherein a length of the fourth conductive layer in the channel length direction of the oxide semiconductor layer is larger than a length of the second conductive layer in the channel length direction of the oxide semiconductor layer.
2. The semiconductor device according to claim 1 ,
wherein the third conductive layer includes titanium, and
wherein the fourth conductive layer includes titanium.
3. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises gallium.
4. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer is formed by using a target obtained by mixing indium oxide, gallium oxide, and zinc oxide and performing sintering of the mixture of indium oxide, gallium oxide, and zinc oxide.
5. The semiconductor device according to claim 1 , wherein each of the third conductive layer and the fourth conductive layer has n-type conductivity.
6. The semiconductor device according to claim 1 ,
wherein the insulating layer overlaps the gate electrode,
wherein the insulating layer does not overlap a region of the oxide semiconductor layer, and
wherein the region of the oxide semiconductor layer does not overlap the gate electrode.
7. The semiconductor device according to claim 1 , wherein the second gate insulating layer contains excessive oxygen.
8. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer contains excessive oxygen.
9. The semiconductor device according to claim 1 , wherein each of the third conductive layer and the fourth conductive layer includes oxygen.
10. The semiconductor device according to claim 1 , wherein each of the third conductive layer and the fourth conductive layer includes metal oxide.
11. The semiconductor device according to claim 1 , wherein each of the third conductive layer and the fourth conductive layer is a buffer layer.
12. A semiconductor device comprising:
a gate electrode including copper;
a first gate insulating layer over the gate electrode, the first gate insulating layer including silicon and nitrogen;
a second gate insulating layer over the first gate insulating layer, the second gate insulating layer including silicon and oxygen;
an oxide semiconductor layer over and in direct contact with the second gate insulating layer, the oxide semiconductor layer comprising indium and zinc;
an insulating layer over a channel formation region of the oxide semiconductor layer, the insulating layer including silicon and oxygen;
a first conductive layer over the oxide semiconductor layer, the first conductive layer including copper;
a second conductive layer over the oxide semiconductor layer, the second conductive layer including copper;
a third conductive layer between the oxide semiconductor layer and the first conductive layer; and
a fourth conductive layer between the oxide semiconductor layer and the second conductive layer,
wherein the oxide semiconductor layer includes a first region and a second region,
wherein the first region includes a first top surface of the oxide semiconductor layer and a first bottom surface of the oxide semiconductor layer, and is in direct contact with the insulating layer,
wherein the second region includes a second top surface of the oxide semiconductor layer and a second bottom surface of the oxide semiconductor layer,
wherein the first conductive layer overlaps the second region,
wherein a thickness of the second region is smaller than a thickness of the first region,
wherein the gate electrode has a light-shielding property,
wherein a length of the third conductive layer in a channel length direction of the oxide semiconductor layer is larger than a length of the first conductive layer in the channel length direction of the oxide semiconductor layer, and
wherein a length of the fourth conductive layer in the channel length direction of the oxide semiconductor layer is larger than a length of the second conductive layer in the channel length direction of the oxide semiconductor layer.
13. The semiconductor device according to claim 12 ,
wherein the third conductive layer includes titanium, and
wherein the fourth conductive layer includes titanium.
14. The semiconductor device according to claim 12 , wherein the oxide semiconductor layer comprises gallium.
15. The semiconductor device according to claim 12 , wherein the oxide semiconductor layer is formed by using a target obtained by mixing indium oxide, gallium oxide, and zinc oxide and performing sintering of the mixture of indium oxide, gallium oxide, and zinc oxide.
16. The semiconductor device according to claim 12 , wherein each of the third conductive layer and the fourth conductive layer has n-type conductivity.
17. The semiconductor device according to claim 12 ,
wherein the insulating layer overlaps the gate electrode,
wherein the insulating layer does not overlap a region of the oxide semiconductor layer, and
wherein the region of the oxide semiconductor layer does not overlap the gate electrode.
18. The semiconductor device according to claim 12 , wherein the second gate insulating layer contains excessive oxygen.
19. The semiconductor device according to claim 12 , wherein the oxide semiconductor layer contains excessive oxygen.
20. The semiconductor device according to claim 12 , wherein each of the third conductive layer and the fourth conductive layer includes oxygen.
21. The semiconductor device according to claim 12 , wherein each of the third conductive layer and the fourth conductive layer includes metal oxide.
22. The semiconductor device according to claim 12 , wherein each of the third conductive layer and the fourth conductive layer is a buffer layer.
23. A semiconductor device comprising:
a gate electrode including copper;
a first gate insulating layer over the gate electrode, the first gate insulating layer including silicon and nitrogen;
a second gate insulating layer over the first gate insulating layer, the second gate insulating layer including silicon and oxygen;
an oxide semiconductor layer over and in direct contact with the second gate insulating layer, the oxide semiconductor layer comprising indium and zinc;
an insulating layer over a channel formation region of the oxide semiconductor layer, the insulating layer including silicon and oxygen;
a first conductive layer over the oxide semiconductor layer, the first conductive layer including copper;
a second conductive layer over the oxide semiconductor layer, the second conductive layer including copper;
a third conductive layer between the oxide semiconductor layer and the first conductive layer; and
a fourth conductive layer between the oxide semiconductor layer and the second conductive layer,
wherein the oxide semiconductor layer includes a first region and a second region,
wherein the first region includes a first top surface of the oxide semiconductor layer and a first bottom surface of the oxide semiconductor layer, and is in direct contact with the insulating layer,
wherein the second region includes a second top surface of the oxide semiconductor layer and a second bottom surface of the oxide semiconductor layer,
wherein the first conductive layer overlaps the second region,
wherein a thickness of the second region is smaller than a thickness of the first region,
wherein the gate electrode has a light-shielding property,
wherein each of the first gate insulating layer and the second gate insulating layer has a light-transmitting property,
wherein a length of the third conductive layer in a channel length direction of the oxide semiconductor layer is larger than a length of the first conductive layer in the channel length direction of the oxide semiconductor layer, and
wherein a length of the fourth conductive layer in the channel length direction of the oxide semiconductor layer is larger than a length of the second conductive layer in the channel length direction of the oxide semiconductor layer.
24. The semiconductor device according to claim 23 ,
wherein the third conductive layer includes titanium, and
wherein the fourth conductive layer includes titanium.
25. The semiconductor device according to claim 23 , wherein the oxide semiconductor layer comprises gallium.
26. The semiconductor device according to claim 23 , wherein the oxide semiconductor layer is formed by using a target obtained by mixing indium oxide, gallium oxide, and zinc oxide and performing sintering of the mixture of indium oxide, gallium oxide, and zinc oxide.
27. The semiconductor device according to claim 23 , wherein each of the third conductive layer and the fourth conductive layer has n-type conductivity.
28. The semiconductor device according to claim 23 ,
wherein the insulating layer overlaps the gate electrode,
wherein the insulating layer does not overlap a region of the oxide semiconductor layer, and
wherein the region of the oxide semiconductor layer does not overlap the gate electrode.
29. The semiconductor device according to claim 23 , wherein the second gate insulating layer contains excessive oxygen.
30. The semiconductor device according to claim 23 , wherein the oxide semiconductor layer contains excessive oxygen.
31. The semiconductor device according to claim 23 , wherein each of the third conductive layer and the fourth conductive layer includes oxygen.
32. The semiconductor device according to claim 23 , wherein each of the third conductive layer and the fourth conductive layer includes metal oxide.
33. The semiconductor device according to claim 23 , wherein each of the third conductive layer and the fourth conductive layer is a buffer layer.
34. A semiconductor device comprising:
a substrate including glass;
a gate electrode over the substrate, the gate electrode including copper;
a first gate insulating layer over the gate electrode, the first gate insulating layer including silicon and nitrogen;
a second gate insulating layer over the first gate insulating layer, the second gate insulating layer including silicon and oxygen;
an oxide semiconductor layer over and in direct contact with the second gate insulating layer, the oxide semiconductor layer comprising indium, gallium and zinc;
an insulating layer over a channel formation region of the oxide semiconductor layer, the insulating layer including silicon and oxygen;
a first conductive layer over the oxide semiconductor layer, the first conductive layer including copper;
a second conductive layer over the oxide semiconductor layer, the second conductive layer including copper;
a third conductive layer between the oxide semiconductor layer and the first conductive layer; and
a fourth conductive layer between the oxide semiconductor layer and the second conductive layer,
wherein the oxide semiconductor layer includes a first region and a second region,
wherein the first region includes a first top surface of the oxide semiconductor layer and a first bottom surface of the oxide semiconductor layer, and is in direct contact with the insulating layer,
wherein the second region includes a second top surface of the oxide semiconductor layer and a second bottom surface of the oxide semiconductor layer,
wherein the first conductive layer overlaps the second region,
wherein a thickness of the second region is smaller than a thickness of the first region,
wherein a length of the third conductive layer in a channel length direction of the oxide semiconductor layer is larger than a length of the first conductive layer in the channel length direction of the oxide semiconductor layer,
wherein a length of the fourth conductive layer in the channel length direction of the oxide semiconductor layer is larger than a length of the second conductive layer in the channel length direction of the oxide semiconductor layer,
wherein the third conductive layer includes titanium, and
wherein the fourth conductive layer includes titanium.
35. The semiconductor device according to claim 34 , wherein the oxide semiconductor layer is formed by using a target obtained by mixing indium oxide, gallium oxide, and zinc oxide and performing sintering of the mixture of indium oxide, gallium oxide, and zinc oxide.
36. The semiconductor device according to claim 34 , wherein each of the third conductive layer and the fourth conductive layer has n-type conductivity.
37. The semiconductor device according to claim 34 ,
wherein the insulating layer overlaps the gate electrode,
wherein the insulating layer does not overlap a region of the oxide semiconductor layer, and
wherein the region of the oxide semiconductor layer does not overlap the gate electrode.
38. The semiconductor device according to claim 34 , wherein the second gate insulating layer contains excessive oxygen.
39. The semiconductor device according to claim 34 , wherein the oxide semiconductor layer contains excessive oxygen.
40. The semiconductor device according to claim 34 , wherein each of the third conductive layer and the fourth conductive layer includes oxygen.
41. The semiconductor device according to claim 34 , wherein each of the third conductive layer and the fourth conductive layer includes metal oxide.
42. The semiconductor device according to claim 34 , wherein each of the third conductive layer and the fourth conductive layer is a buffer layer.