Techniques for forming non-planar germanium quantum well devices
Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
1. A semiconductor device, comprising:
a body of germanium having a top surface and a bottom surface opposite the top surface, and opposing sidewalls between the top and bottom surfaces, and the bottom surface of the body of germanium is on a first semiconductor material having a higher band gap than germanium;
a second semiconductor material in contact with the top surface and the sidewalls of the body of germanium, the second semiconductor material having a higher band gap than germanium; and
a gate structure over at least a portion of the second semiconductor material, the gate structure comprising a gate electrode and a gate dielectric, the gate dielectric between the gate electrode and the second semiconductor material, the gate dielectric being distinct from and in contact with the second semiconductor material.
2. The device of claim 1 , wherein the second semiconductor material consists essentially of silicon, or silicon and germanium.
3. The device of claim 1 wherein the first semiconductor material is part of a semiconductor structure that includes one or more layers, and a first sidewall of the semiconductor structure is adjacent a first isolation region, and a second sidewall of the semiconductor structure is adjacent a second isolation region, the first and second isolation regions each having upper and lower surfaces.
4. The device of claim 3 wherein the semiconductor structure includes one or more graded semiconductor components.
5. The device of claim 3 wherein at least one of the gate dielectric and the gate electrode are on the upper surface of the first isolation region and the upper surface of the second isolation region, and the lower surfaces of the first and second isolation regions are on the semiconductor structure.
6. The device of claim 3 wherein the semiconductor structure includes a region containing a p-type or n-type dopant.
7. The device of claim 6 wherein, in addition to the p-type dopant or the n-type dopant, the first semiconductor material consists essentially of silicon and germanium.
8. The device of claim 1 wherein the first semiconductor material comprises a group III-V semiconductor compound.
9. The device of claim 8 wherein the group III-V semiconductor compound includes at least two of gallium, arsenide, indium, and aluminum.
10. The device of claim 1 further including a source region or drain region.
11. The device of claim 1 further including a source region adjacent a first side of the gate structure, and a drain region adjacent a second side of the gate structure.
12. The device of claim 1 wherein the gate dielectric comprises a high-k gate dielectric material, and the gate electrode is on the high-k gate dielectric material.
13. The device of claim 1 further comprising a silicon substrate.
14. A semiconductor transistor device, comprising:
a first isolation region and a second isolation region, the first and second isolation regions each having opposing upper and lower surfaces;
a germanium fin having a top surface and a bottom surface opposite the top surface, and opposing sidewalls between the top and bottom surfaces, and the bottom surface of the germanium fin is on a first semiconductor material having a higher band gap than germanium, wherein the first semiconductor material is part of a semiconductor structure that includes one or more layers, and a first sidewall of the semiconductor structure is adjacent the first isolation region, and a second sidewall of the semiconductor structure is adjacent the second isolation region, and wherein the semiconductor structure includes a region containing a p-type impurity or an n-type impurity;
a second semiconductor material in contact with the top surface and the sidewalls of the germanium fin, the second semiconductor material having a higher band gap than germanium;
a gate structure over at least a portion of the second semiconductor material, the gate structure comprising a gate electrode and a gate dielectric, the gate dielectric between the gate electrode and the second semiconductor material, the gate dielectric comprising a high-k dielectric material and being distinct from and in contact with the second semiconductor material, and the gate electrode being on the high-k gate dielectric material, wherein at least one of the gate dielectric and the gate electrode are on the upper surface of the first isolation region and the upper surface of the second isolation region, and the lower surfaces of the first and second isolation regions are on the semiconductor structure; and
a source region or drain region.
15. The device of claim 14 , wherein the second semiconductor material consists essentially of silicon, or silicon and germanium.
16. The device of claim 14 wherein the semiconductor structure includes one or more graded components.
17. The device of claim 14 wherein, in addition to the p-type impurity or the n-type impurity, the first semiconductor material consists essentially of silicon and germanium.
18. The device of claim 14 wherein the first semiconductor material comprises a group III-V semiconductor compound.
19. The device of claim 18 wherein the group III-V semiconductor compound includes at least two of gallium, arsenide, indium, and aluminum.
20. The device of claim 14 further comprising a silicon substrate.