Advanced lithography and self-assembled devices
Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.
1. A method of fabricating an integrated circuit structure, the method comprising:
forming a plurality of backbone features above a semiconductor substrate, a semiconductor layer, or a stack of semiconductor layers;
forming a first set of spacers along sidewalls of each of the plurality of backbone features, the first set of spacers having a first material composition different than a material composition of the plurality of backbone features;
forming a second set of spacers along sidewalls of each of the first set of spacers, the second set of spacers having a second material composition different than the first material composition and different than the material composition of the plurality of backbone features;
subsequent to forming the second set of spacers, removing the plurality of backbone features;
subsequent to removing the plurality of backbone features, forming a third set of spacers along sidewalls of each of the first set of spacers, the third set of spacers having the second material composition;
forming a final feature in each opening between adjacent pairs of spacers of the third set of spacers;
planarizing the first set of spacers, the second set of spacers, the third set of spacers, and the final features to form a target foundation layer; and
using the target foundation layer to form a plurality of fins or three-dimensional bodies in the semiconductor substrate, the semiconductor layer, or the stack of semiconductor layers.
2. The method of claim 1 , wherein forming the plurality of backbone features comprises using a standard lithography operation.
3. The method of claim 1 , wherein forming the plurality of backbone features comprises forming a plurality of features comprising a material selected from the group consisting of silicon nitride, silicon oxide and silicon carbide.
4. The method of claim 1 , wherein forming the first set of spacers comprises:
depositing a material of the first set of spacers conformal with the plurality of backbone features using an atomic layer deposition (ALD) process; and
anisotropically etching the material of the first set of spacers to form the first set of spacers along the sidewalls of each of plurality of backbone features.
5. The method of claim 1 , wherein forming the first set of spacers comprises selectively growing a material of the first set of spacers along the sidewalls of each of plurality of backbone features.
6. The method of claim 1 , wherein each final feature has a lateral width greater than a lateral width of each spacer from the first set of spacers, the second set of spacers, and the third set of spacers.
7. The method of claim 1 , wherein each final feature is formed by a merging of material growth formed along adjacent pairs of spacers of the third set of spacers.
8. The method of claim 1 , wherein each final feature comprises a third material composition.
9. The method of claim 1 , wherein using the target foundation layer to form the metallization layer of the semiconductor structure comprises:
removing all portions of the first material composition to form a first plurality of trenches; and
forming a first plurality of conductive lines in the first plurality of trenches.
10. The method of claim 9 , wherein using the target foundation layer to form the metallization layer of the semiconductor structure further comprises:
forming a second plurality of trenches; and
forming a second plurality of conductive lines in the second plurality of trenches.
11. The method of claim 10 , wherein the first plurality of conductive lines and the second plurality of conductive lines are of a same composition.
12. The method of claim 10 , wherein the first plurality of conductive lines and the second plurality of conductive lines are of a different composition.
13. The method of claim 1 , further comprising forming additional sets of spacers between forming the second set of spacers and the third set of spacers, and prior to removing the plurality of backbone features.
14. A method of fabricating an integrated circuit structure, the method comprising:
forming a plurality of backbone features above a semiconductor substrate, a semiconductor layer, or a stack of semiconductor layers;
forming a first set of spacers along sidewalls of each of the plurality of backbone features, the first set of spacers having a first material composition different than a material composition of the plurality of backbone features;
forming a second set of spacers along sidewalls of each of the first set of spacers, the second set of spacers having a second material composition different than the first material composition and different than the material composition of the plurality of backbone features;
forming a third set of spacers along sidewalls of each of the second set of spacers, the third set of spacers having a third material composition different than the first material composition, different than the second material composition, and different than the material composition of the plurality of backbone features;
forming a fourth set of spacers along sidewalls of each of the third set of spacers, the fourth set of spacers having the second material composition;
forming a fifth set of spacers laterally adjacent to sidewalls of each of the fourth set of spacers, the fifth set of spacers having the first material composition;
subsequent to forming the fifth set of spacers, removing the plurality of backbone features;
subsequent to removing the plurality of backbone features, forming a sixth set of spacers along sidewalls of each of the first set of spacers and along sidewalls of each of the fifth set of spacers, the sixth set of spacers having the second material composition;
forming a final feature in each opening between adjacent pairs of spacers of the sixth set of spacers;
planarizing the first set of spacers, the second set of spacers, the third set of spacers, the fourth set of spacers, the fifth set of spacers, the sixth set of spacers, and the final features to form a target foundation layer; and
using the target foundation layer to form a plurality of fins or three-dimensional bodies in the semiconductor substrate, the semiconductor layer, or the stack of semiconductor layers.
15. The method of claim 14 , wherein forming the plurality of backbone features comprises using a standard lithography operation.
16. The method of claim 14 , wherein forming the plurality of backbone features comprises forming a plurality of features comprising a material selected from the group consisting of silicon nitride, silicon oxide and silicon carbide.
17. The method of claim 14 , wherein forming the first set of spacers comprises:
depositing a material of the first set of spacers conformal with the plurality of backbone features using an atomic layer deposition (ALD) process; and
anisotropically etching the material of the first set of spacers to form the first set of spacers along the sidewalls of each of plurality of backbone features.
18. The method of claim 14 , wherein forming the first set of spacers comprises selectively growing a material of the first set of spacers along the sidewalls of each of plurality of backbone features.
19. The method of claim 14 , wherein each final feature has a lateral width greater than a lateral width of each spacers from the first set of spacers, the second set of spacers, the third set of spacers, the fourth set of spacers, the fifth set of spacers, and the sixth set of spacers.
20. The method of claim 14 , wherein each final feature is formed by a merging of material growth formed along adjacent pairs of spacers of the sixth set of spacers.