MISHFET and Schottky device integration
A semiconductor device includes a substrate comprising a heterostructure configured to support formation of a channel during operation, first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate, a gate supported by the substrate, disposed in a first opening in the first dielectric layer, and to which a bias voltage is applied during operation to control current flow through the channel, the second dielectric layer being disposed between the gate and the substrate, and an electrode supported by the substrate, disposed in a second opening in the first and second dielectric layers, and configured to establish a Schottky junction with the substrate.
1. A semiconductor device comprising: a substrate; first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate; a gate comprising a second metal layer supported by the substrate and disposed in a first opening in the first dielectric layer, the second dielectric layer being disposed between the gate and the substrate to form a metal-insulator gate configuration at a surface of the substrate; an electrode comprising a first metal layer, supported by the substrate, disposed in a second opening in the first and second dielectric layers, and disposed at the surface of the substrate and configured to establish a Schottky junction with the substrate; an inter-layer dielectric layer disposed over the electrode and first and second dielectric layers, wherein the gate is disposed within an opening in the inter-layer dielectric layer; and a field plate supported by the substrate, separate and distinct from the electrode, disposed adjacent the electrode, wherein the field plate comprises the second metal layer, and wherein the inter-layer dielectric layer is disposed between the field plate and the electrode.
2. The semiconductor device of claim 1 , further comprising a further electrode supported by the substrate, disposed in a third opening in the first and second dielectric layers, configured to define an ohmic contact with the substrate, and spaced from the gate to define a current electrode of a metal-insulator-semiconductor heterojunction field effect transistor (MISHFET) structure comprising the gate.
3. The semiconductor device of claim 1 , further comprising:
a first pair of current electrodes supported by the substrate, spaced from the electrode, and configured to define a heterojunction field effect transistor (HFET) structure comprising the Schottky junction; and
a second pair of current electrodes supported by the substrate, spaced from the gate, and configured to define a metal-insulator-semiconductor HFET (MISHFET) structure comprising the gate.
4. The semiconductor device of claim 3 , wherein the HFET and MISHFET structures are coupled to one another in a cascode configuration.
5. The semiconductor device of claim 3 , wherein the HFET and MISHFET structures are coupled to one another in a Doherty power amplifier circuit.
6. The semiconductor device of claim 1 , further comprising first and second current electrodes supported by the substrate and spaced laterally outward from the Schottky junction and the gate to define a multiple-gate field effect transistor (FET) structure comprising the electrode and the gate.
7. The semiconductor device of claim 6 , further comprising a current region in the substrate, disposed between the Schottky junction and the gate, and shared by FET structures of the multiple-gate FET structure.
8. The semiconductor device of claim 6 , wherein the multiple-gate FET structure is configured as a dual-gate FET cascode amplifier.
9. The semiconductor device of claim 1 , further comprising a current electrode supported by the substrate, spaced from the gate, and configured to define a metal-insulator-semiconductor heterojunction field effect transistor (MISHFET) structure comprising the gate, the current electrode, and a first current region in the substrate, wherein: the current electrode is disposed in a third opening in the first and second dielectric layers and is configured to define an ohmic contact with the first current region; and the Schottky junction is spaced from the gate and the current electrode.
10. The semiconductor device of claim 9 , wherein the second dielectric layer comprises Fluorine-doped aluminum oxide such that the MISHFET structure is configured as a quasi-enhancement mode device.
11. The semiconductor device of claim 1 , further comprising a current electrode supported by the substrate, spaced from the gate, disposed in a third opening in the first and second dielectric layers, and configured to define an ohmic contact with the substrate, wherein the current electrode and the electrode that establishes the Schottky junction are spaced from the gate to define a heterojunction field effect transistor (HFET).
12. The semiconductor device of claim 1 , wherein the second dielectric layer comprises a material having an etch selectivity to block an etchant of the first dielectric layer from reaching the surface of the substrate.
13. An electronic apparatus comprising: a substrate; first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate; a gate comprising a second metal layer, supported by the substrate, positioned in a first opening in the first dielectric layer, and disposed in a metal-insulator-semiconductor heterojunction field effect transistor (MISHFET) arrangement, the second dielectric layer being disposed between the gate and the substrate; an electrode comprising a first metal layer, supported by the substrate, disposed in a second opening in the first and second dielectric layers, and configured to establish a Schottky junction with the substrate; an inter-layer dielectric layer disposed over the electrode and first and second dielectric layers, wherein the gate is disposed within an opening in the inter-layer dielectric layer; and a field plate supported by the substrate, separate and distinct from the electrode, and disposed adjacent the electrode, wherein the field plate comprises the second metal layer, and wherein the inter-layer dielectric layer is disposed between the field plate and the electrode.
14. The electronic apparatus of claim 13 , further comprising:
a first pair of current electrodes supported by the substrate, spaced from the electrode, and configured to define a heterojunction field effect transistor (HFET) structure comprising the Schottky junction; and
a second pair of current electrodes supported by the substrate and spaced from the gate and configured to define a MISHFET structure of the MISHFET arrangement, the MISHFET structure comprising the gate.
15. The electronic apparatus of claim 14 , wherein the HFET and MISHFET structures are coupled to one another in a cascode configuration or to form a Doherty power amplifier.
16. The electronic apparatus of claim 13 , further comprising first and second current electrodes supported by the substrate and spaced laterally outward from the Schottky junction and the gate to define a multiple-gate field effect transistor (FET) structure comprising the electrode and the gate.
17. The electronic apparatus of claim 13 , further comprising a current electrode supported by the substrate, spaced from the gate, disposed in a third opening in the first and second dielectric layers, and configured to define an ohmic contact with the substrate, wherein the current electrode and the electrode that establishes the Schottky junction are spaced from the gate to define the MISHFET arrangement.
18. The electronic apparatus of claim 13 , further comprising: a current electrode supported by the substrate, spaced from the gate, disposed in a third opening in the first and second dielectric layers, and configured to define an ohmic contact with the substrate.
19. A semiconductor device comprising: a substrate comprising a heterostructure configured to support formation of a channel during operation; first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate; a gate comprising a first metal layer supported by the substrate and disposed in a first opening in the first dielectric layer, the second dielectric layer being disposed between the gate and the substrate to form a metal-insulator gate configuration at a surface of the substrate; a gate electrode comprising a second metal layer, supported by the substrate, disposed in a second opening in the first and second dielectric layers, and disposed at the surface of the substrate and configured to establish a Schottky junction with the substrate; and an inter-layer dielectric layer disposed over the gate electrode and first and second dielectric layers, wherein the gate is disposed within an opening in the inter-layer dielectric layer, and wherein a portion of the gate is over a portion of the inter-layer dielectric layer.
20. The semiconductor device of claim 19 , further comprising a further electrode supported by the substrate, disposed in a third opening in the first and second dielectric layers, configured to define an ohmic contact with the substrate, and spaced from the gate to define a current electrode of a metal-insulator-semiconductor heterojunction field effect transistor (MISHFET) structure comprising the gate.
21. The semiconductor device of claim 19 , further comprising: a first pair of current electrodes supported by the substrate, spaced from the gate electrode, and configured to define a heterojunction field effect transistor (HFET) structure comprising the Schottky junction; and a second pair of current electrodes supported by the substrate, spaced from the gate, and configured to define a metal-insulator-semiconductor HFET (MISHFET) structure comprising the gate.
22. The semiconductor device of claim 19 , further comprising a current electrode supported by the substrate, spaced from the gate, and configured to define a MISHFET structure, the MISHFET structure comprising the gate, the current electrode, and a first current region in the substrate, wherein: the current electrode is disposed in a third opening of the first and second dielectric layers and is configured to define an ohmic contact with the first current region; and the Schottky junction is spaced from the gate and the current electrode.