Three-dimensional array device having a metal containing barrier and method of making thereof
A three-dimensional memory device includes driver transistors containing boron doped semiconductor active regions, device contact via structures in physical contact with the boron doped semiconductor active regions, the device contact via structures containing at least one of tantalum, tungsten, and cobalt, and a three-dimensional memory array located over the driver transistors and including an alternating stack of insulating layers and electrically conductive layers and memory structures vertically extending through the alternating stack.
1. A three-dimensional memory device, comprising:
driver transistors containing boron doped semiconductor active regions;
device contact via structures in physical contact with the boron doped semiconductor active regions, the device contact via structures containing at least one of tantalum, titanium, tungsten, and cobalt; and
a three-dimensional memory array located over the driver transistors and comprising an alternating stack of insulating layers and electrically conductive layers and memory structures vertically extending through the alternating stack,
wherein:
each device contact via structure comprises from bottom to top, a metal-semiconductor alloy portion, a metallic nitride barrier layer and a conductive fill material portion; and
the at least one of tantalum, titanium, tungsten, and cobalt is present in at least one of the metal-semiconductor alloy portion, the metallic nitride barrier layer, or between the metal-semiconductor alloy portion and the metallic nitride barrier layer.
2. The three-dimensional memory device of claim 1 , wherein:
the at least one of tantalum, titanium, tungsten, and cobalt is present in the metal-semiconductor alloy portion; and
the metal-semiconductor alloy portion comprises tantalum silicide, cobalt silicide, tungsten silicide, or tantalum cobalt silicide.
3. The three-dimensional memory device of claim 1 , further comprising an elemental metal layer including cobalt, tantalum, and/or tungsten and located between the metal-semiconductor alloy portion and the metallic nitride barrier layer, wherein at least one of cobalt, tantalum, and tungsten is present between the metal-semiconductor alloy portion and the metallic nitride barrier layer.
4. The three-dimensional memory device of claim 1 , wherein the metallic nitride barrier layer comprises a material selected from tantalum nitride, titanium nitride, and tungsten nitride.
5. The three-dimensional memory device of claim 1 , wherein tantalum is present in the metallic nitride barrier layer and the metallic nitride barrier layer comprises tantalum nitride.
6. The three-dimensional memory device of claim 5 , wherein the metal-semiconductor alloy portion comprises a material selected from one of titanium silicide, cobalt silicide and tantalum silicide.
7. The three-dimensional memory device of claim 5 , further comprising an additional titanium nitride barrier layer.
8. The three-dimensional memory device of claim 1 , further comprising a set of conductive structures which includes the device conductive via structure, which provides an electrically conductive path between the boron doped semiconductor active regions and a metal line located above a horizontal plane including a top surface of the three-dimensional memory array.
9. The three-dimensional memory device of claim 8 , wherein each of the memory structures comprises a memory film and a vertical semiconductor channel, and wherein the electrically conductive layers comprise word lines of the three-dimensional memory array.
10. The three-dimensional memory device of claim 9 , wherein the set of conductive structures and the metal line provide an electrically conductive path between the boron doped semiconductor active regions of the driver transistors and the word lines of the three-dimensional memory array.
11. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory array comprises a monolithic three-dimensional NAND memory device;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
a substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;
the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.
12. A method of forming a three-dimensional memory device, comprising:
forming driver transistors containing boron doped semiconductor active regions;
forming device contact via structures in physical contact with the boron doped semiconductor active regions, the device contact via structures containing at least one of cobalt, tantalum, and tungsten; and
forming a three-dimensional memory array located over the driver transistors and comprising an alternating stack of insulating layers and electrically conductive layers and memory structures vertically extending through the alternating stack,
wherein the method comprises at least one feature selected from:
a first feature that the method further comprises subjecting the three-dimensional memory device to a dopant activation anneal process, wherein the at least one of cobalt, tantalum, and tungsten present within the device contact via structure blocks diffusion of boron out of the boron doped semiconductor active regions during the dopant activation anneal process; and
a second feature that each device contact via structure comprises from bottom to top, a metal-semiconductor alloy portion, a metallic nitride barrier layer and a conductive fill material portion, and the at least one of cobalt, tantalum, and tungsten is present in at least one of the metal-semiconductor alloy portion, the metallic nitride barrier layer, or between the metal-semiconductor alloy portion and the metallic nitride barrier layer.
13. The method of claim 12 , wherein the method comprises the first feature.
14. The method of claim 12 , wherein the method comprises the second feature.
15. The method of claim 14 , wherein:
the boron doped semiconductor active regions comprise boron doped silicon transistor source or drain regions;
the at least one of tantalum or cobalt is present in the metal-semiconductor alloy portion; and
the metal-semiconductor alloy portion comprises tantalum silicide, tungsten silicide, cobalt silicide, or tantalum cobalt silicide formed by reacting a tantalum layer, a cobalt layer, a tungsten layer, or a tantalum cobalt alloy layer with boron doped silicon of the transistor source or drain regions.
16. The method of claim 14 , further comprising forming an elemental metal layer including at least one of cobalt, tantalum, and tungsten between the metal-semiconductor alloy portion and the metallic nitride barrier layer, wherein the at least one of cobalt, tantalum, and tungsten is present between the metal-semiconductor alloy portion and the metallic nitride barrier layer.
17. The method of claim 14 , wherein tantalum is present in the metallic nitride barrier layer, and the metallic nitride barrier layer comprises tantalum nitride.
18. The method of claim 12 , further comprising forming set of conductive structures which includes the device conductive via structure, and forming a metal line located above a horizontal plane including a top surface of the three-dimensional memory array.
19. The method of claim 18 , wherein:
the set of conductive structures provides an electrically conductive path between the boron doped semiconductor active regions and the metal line;
each of the memory structures comprises a memory film and a vertical semiconductor channel;
the electrically conductive layers comprise word lines of the three-dimensional memory array; and
the set of conductive structures and the metal line provide an electrically conductive path between the boron doped semiconductor active regions of the driver transistors and the word lines of the three-dimensional memory array.
20. The method of claim 12 , wherein:
the three-dimensional memory array comprises a monolithic three-dimensional NAND memory device;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
a substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;
the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.