Multi-tier memory device with through-stack peripheral contact via structures and method of making thereof
Contacts to peripheral devices extending through multiple tier structures of a three-dimensional memory device can be formed with minimal additional processing steps. First peripheral via cavities through a first tier structure can be formed concurrently with formation of first memory openings. Sacrificial via fill structures can be formed in the first peripheral via cavities concurrently with formation of sacrificial memory opening fill structures that are formed in the first memory openings. Second peripheral via cavities through a second tier structure can be formed concurrently with formation of word line contact via cavities that extend to top surfaces of electrically conductive layers in the first and second tier structures. After removal of the sacrificial via fill structures, the first and second peripheral via cavities can be filled with a conductive material to form peripheral contact via structures concurrently with formation of word line contact via structures.
1. A method of forming a semiconductor structure, comprising:
forming peripheral devices on a semiconductor substrate;
forming a first tier structure including a first active alternating stack and a first peripheral alternating stack over the semiconductor substrate, wherein at least the first peripheral alternating stack overlies the peripheral devices, and each of the first active alternating stack and the first peripheral alternating stack comprises an alternating stack of first insulating layers and first spacer material layers patterned to provide respective first stepped terraces;
forming first peripheral via cavities through the first peripheral alternating stack;
filling the first peripheral via cavities with sacrificial via fill structures;
forming a second tier structure including a second active alternating stack and a second peripheral alternating stack over the first tier structure, wherein each of the second active alternating stack and the second peripheral alternating stack comprises an alternating stack of second insulating layers and second spacer material layers patterned to provide respective second stepped terraces, the second active alternating stack overlies the first active alternating stack, and the second peripheral alternating stack overlies the first peripheral alternating stack;
replacing at least a portion of the first and second spacer material layers in the first and second active alternating stacks with electrically conductive layers; and
concurrently forming second peripheral via cavities extending to the peripheral via fill structures through the second peripheral alternating stack and word line contact via cavities extending to the electrically conductive layers in the first and second active alternating stacks.
2. The method of claim 1 , further comprising:
removing the sacrificial via fill structures; and
concurrently forming peripheral via structures in volumes of the first and second peripheral via cavities and word line contact via structures in the word line contact via cavities.
3. The method of claim 1 , wherein replacement of the portions of the first and second spacer material layers in the first and second active alternating stacks with the electrically conductive layers is performed without removing portions of the first and second spacer material layers in the first and second peripheral alternating stacks.
4. The method of claim 3 , wherein the first and second spacer material layers comprise a dielectric material different from materials of the first and second insulating layers.
5. The method of claim 1 , further comprising forming a semiconductor material layer above a level of the peripheral devices, wherein the first tier structure is formed over the semiconductor material layer.
6. The method of claim 5 , further comprising forming lower level metal interconnect structures embedded in at least lower level dielectric layer over the peripheral devices, wherein the semiconductor material layer is formed on the at least one lower level dielectric layer, wherein the first peripheral via cavities are formed by an anisotropic etch process that employs a subset of the lower level metal interconnect structures as an etch stop structure.
7. The method of claim 5 , wherein the semiconductor material layer is formed on a top surface of the semiconductor substrate in a region in which the peripheral devices are not present.
8. The method of claim 7 , further comprising forming a dielectric metal oxide etch stop layer over the peripheral devices, wherein the first peripheral via cavities are formed by an anisotropic etch process that employs a portion of the dielectric metal oxide etch stop layer as an etch stop structure.
9. The method of claim 1 , wherein:
the second stepped terraces of the second peripheral alternating stack overlie an area of the first stepped terraces of the first peripheral alternating stack; and
the second stepped terraces of the second active alternating stack are located outside an entire area of the first stepped terraces of the first active alternating stack.
10. The method of claim 1 , further comprising:
forming first memory openings through the first active alternating stack concurrently with formation of the first peripheral via cavities; and
forming sacrificial memory opening fill structures in the first memory openings concurrently with formation of sacrificial via fill structures.
11. The method of claim 10 , further comprising:
forming second memory openings through the second active alternating stack and over the sacrificial memory opening fill structures;
removing the sacrificial memory opening fill structures; and
forming memory stack structures in volumes of the first and second memory openings;
wherein there are no memory stack structures located in the first and the second peripheral alternating stacks; and
wherein each of the memory stack structures comprises:
a vertical stack of memory elements located at each level of the first and second electrically conductive layers;
a tunneling dielectric layer vertically extending through the first and second active alternating stacks; and
a vertical semiconductor channel located on the tunneling dielectric layer and extending through the first and second active alternating stacks.
12. The method of claim 1 , wherein:
the first active alternating stack of first insulating layers and first spacer material layers is patterned using a mask which exposes only a region of the respective first stepped terraces on two opposing sides of the first tier structure facing a portion of the peripheral devices which comprise word line decoder circuitry; and
no stepped terraces are formed on additional sides of the first tier structure facing a portion of the peripheral devices which comprise bit line decoder circuitry.
13. The method of claim 12 , wherein the first and second electrically conductive layers of the respective first and second active alternating stacks contact respective first and second spacer material layers of the respective first and second peripheral alternating stacks in an area of the first and second active alternating stacks facing the portion of the peripheral devices which comprise the bit line decoder circuitry.
14. The method of claim 1 , wherein:
the semiconductor device is a monolithic three-dimensional memory device comprising a vertical NAND device located over the semiconductor substrate;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the vertical NAND device;
the semiconductor substrate comprises a silicon substrate;
the vertical NAND device comprises an array of monolithic three-dimensional NAND strings located over the silicon substrate;
at least one memory cell in a first device level of the three-dimensional array of NAND strings is located over another memory cell in a second device level of the three-dimensional array of NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the semiconductor substrate;
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the semiconductor substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level.
15. A method of forming a semiconductor structure, comprising:
forming peripheral devices on a semiconductor substrate;
forming a first active alternating stack and a first peripheral alternating stack over the semiconductor substrate, wherein at least the first peripheral alternating stack overlies the peripheral devices, and each of the first active alternating stack and the first peripheral alternating stack comprises an alternating stack of first insulating layers and first spacer material layers patterned to provide respective first stepped terraces;
forming memory openings in the first active alternating stack;
forming memory stack structures in the memory openings in the first active alternating stack, wherein there are no memory stack structures located in the first peripheral alternating stack; and
replacing the first spacer material layers in the first active alternating stack with first electrically conductive layers without replacing the first spacer material layers in the first peripheral stack with the electrically conductive layers;
wherein:
the first active alternating stack of first insulating layers and first spacer material layers is patterned using a mask which exposes only a region of the respective first stepped terraces on two opposing sides of the first active alternating stack facing a portion of the peripheral devices which comprise word line decoder circuitry;
no stepped terraces are formed on additional sides of the first active alternating stack facing a portion of the peripheral devices which comprise bit line decoder circuitry; and
the electrically conductive layers of the first active alternating stack contact respective first spacer material layers of the first peripheral alternating stack in an area of the first active alternating stacks facing the portion of the peripheral devices which comprise the bit line decoder circuitry.