Mid-plane word line switch connection for CMOS under three-dimensional memory device and method of making thereof

1. A method of forming a semiconductor structure, comprising:

forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers;

covering a connection region with a patterned hard mask layer;

applying and patterning a trimmable material layer over the alternating stack, wherein the patterned trimmable material layer covers a first memory array region located on one side of the connection region and a second memory array region located on another side of the connection region, and does not cover a center portion of an intermediate region between the first memory array region and the second memory array region, the intermediate region being adjacent to the connection region;

forming a first terrace region adjoined to the first memory array region at one side of the intermediate region and a second terrace region adjoined to the second memory array region at another side of the intermediate region;

removing the trimmable material layer and the patterned hard mask layer, wherein each of the insulating layers and the spacer material layers within the alternating stack continuously extends between the first and second memory array regions through the connection region; and

forming first memory stack structures in the first memory array region and second memory stack structures in the second memory array region.

2. The method of claim 1 , wherein the first terrace region and the second terrace region are simultaneously formed by iteratively etching the spacer material layers and the insulating layers of the alternating stack and trimming the trimmable material layer.

3. The method of claim 1 , wherein each of the insulating layers and the electrically conductive layers within the alternating stack continuously extends between the first and second memory array regions in the connection region after formation of the electrically conductive layers and after formation of the first and second memory stack structures.

4. The method of claim 1 , wherein:

the first memory array region and the second memory array region are laterally spaced from each other along a first horizontal direction;

the connection region is laterally spaced from the first and second terrace regions along a second horizontal direction that is perpendicular to the first horizontal direction; and

each layer within the alternating stack has a same width along the second horizontal direction within the connection region.

5. The method of claim 1 , further comprising forming contact via structures on a respective one of the electrically conductive layers in the first terrace region and in the second terrace region.

6. The method of claim 5 , further comprising forming a retro-stepped dielectric material portion directly on first stepped surfaces located in the first terrace region and second stepped surfaces located in the second terrace region, wherein the contact via structures are formed through the retro-stepped dielectric material portion.

7. The method of claim 6 , further comprising:

forming semiconductor devices over the substrate;

forming a combination of lower metal interconnect structures and lower dielectric layers that embeds the lower metal interconnect structures over the semiconductor devices, wherein the lower metal interconnect structures are electrically connected to the semiconductor devices; and

forming through-memory-level via structures through the retro-stepped dielectric material portion and on a respective one of the lower metal interconnect structures.

8. The method of claim 7 , further comprising forming additional through-memory-level via structures through the alternating stack in the connection region, wherein the additional through-memory-level via structures are electrically shorted to a respective one of the lower metal interconnect structures.

9. The method of claim 8 , wherein:

the through-memory-level via structures extending through the retro-stepped dielectric material portion extend through less than all layers within the alternating stack;

each of the additional through-memory-level via structures extending through the alternating stack in the connection region extend through each layer within the alternating stack; and

each of the through-memory-level via structures extending through the retro-stepped dielectric material portion and each of the additional through-memory-level via structures are laterally isolated from the electrically conductive layers by a respective insulating liner.

10. The method of claim 8 , further comprising forming upper metal interconnect structures, wherein a subset of the upper metal interconnect structures provide electrically conductive paths between a respective pair of a through-memory-level via structure and a contact via structure.

11. The method of claim 1 , wherein the spacer material layers are formed as sacrificial material layers, and the method further comprises:

forming first and second backside trenches through the alternating stack, wherein the first backside trench straddles the intermediate region, the first memory array region, and the second memory array region, and the second backside trench straddles the connection region, the first memory array region, and the second memory array region; and

removing the sacrificial material layers by introducing an etchant through the pair of backside contact trenches;

wherein:

the first backside trench has a sidewall that contacts a first subset of sidewalls of the alternating stack in the first memory array region, in the second memory array region, in the first terrace region, and in the second terrace region; and

the second backside trench has a sidewall that contacts a second subset of sidewalls of the alternating stack in the first memory array region, in the second memory array region, in the connection region.