Linearity in radio-frequency devices using body impedance control
A process for fabricating a semiconductor die involves providing a semiconductor substrate, forming a first field-effect transistor on the semiconductor substrate, the first field-effect transistor having a source, a drain, a gate, and a body, forming a coupling path that couples the body of the first field-effect transistor to the gate of the first field-effect transistor, the coupling path including a diode, and forming an adjustable impedance network coupled between the body of the first field-effect transistor and a ground reference, the adjustable impedance network being configured to reduce radio-frequency distortion in the first field-effect transistor.
1. A method for fabricating a semiconductor die, the method comprising:
providing a semiconductor substrate;
forming a first field-effect transistor on the semiconductor substrate, the first field-effect transistor having a source, a drain, a gate, and a body;
forming a coupling path that couples the body of the first field-effect transistor to one of the gate, the source, and the drain of the first field-effect transistor, the coupling path including a diode; and
forming an adjustable impedance network coupled between the body of the first field-effect transistor and a ground reference, the adjustable impedance network being configured to reduce radio-frequency distortion in the first field-effect transistor.
2. The method of claim 1 further comprising forming an insulator layer on the semiconductor substrate, the first field-effect transistor being formed over the insulator layer.
3. The method of claim 1 further comprising forming a second field-effect transistor in the adjustable impedance network, the second field-effect transistor having a gate, a drain, and a source, the second field-effect transistor being connected at one of the drain or source of the second field-effect transistor to the body of the first field-effect transistor and connected at another of the drain or source of the second field-effect transistor to the ground reference.
4. The method of claim 3 wherein the adjustable impedance network includes one or more resistors connected in series with the second field-effect transistor.
5. The method of claim 3 wherein the adjustable impedance network includes one or more capacitors connected in series with the second field-effect transistor.
6. The method of claim 3 further comprising operating the second field-effect transistor to provide a desired impedance for reducing undesired radio-frequency distortion in the first field-effect transistor.
7. The method of claim 1 further comprising forming a capacitor in the adjustable impedance network, the capacitor being connected at a first end to the body of the first field-effect transistor and at a second end to the ground reference.
8. The method of claim 1 wherein the adjustable impedance network includes a capacitor connected in series with an inductor.
9. The method of claim 1 wherein the adjustable impedance network includes a plurality of capacitors configured to be selectively coupled to the body of the first field-effect transistor using a network of switches.
10. A method for fabricating a radio-frequency module, the method comprising:
providing a semiconductor substrate;
forming a first field-effect transistor on the semiconductor substrate between a first node and a second node, the first field-effect transistor having a source, a drain, a gate, and a body;
forming a coupling path between the body of the first field-effect transistor and one or more of the gate, the source, and the drain of the first field-effect transistor;
forming a diode in the coupling path; and
forming an adjustable impedance network on the semiconductor substrate between the body of the first field-effect transistor and a ground reference, the adjustable impedance network being configured to reduce radio-frequency distortion in the first field-effect transistor.
11. The method of claim 10 further comprising forming an insulator layer on the semiconductor substrate, the first field-effect transistor being formed over the insulator layer.
12. The method of claim 10 wherein the adjustable impedance network includes a second field-effect transistor having a gate, a drain, and a source, the second field-effect transistor being connected at one of the drain or source of the second field-effect transistor to the body of the first field-effect transistor and connected at another of the drain or source of the second field-effect transistor to the ground reference.
13. The method of claim 10 wherein the adjustable impedance network includes a capacitor connected at a first end to the body of the first field-effect transistor and at a second end to the ground reference.
14. The method of claim 10 wherein the adjustable impedance network includes a capacitor connected in series with an inductor.
15. The method of claim 10 wherein the adjustable impedance network includes a plurality of capacitors configured to be selectively coupled to the body of the first field-effect transistor using a network of switches.