LDMOS finFET structures with shallow trench isolation inside the fin

1. A structure for a field-effect transistor, the structure comprising:

a first fin and a second fin extending vertically from a top surface of a substrate, the first fin separated from the second fin by a cut extending vertically to the top surface of the substrate;

a body region that is arranged partially in the substrate and partially in the first fin, the body region having a first conductivity type;

a drain region that is arranged partially in the substrate, partially in the first fin, and partially in the second fin, the drain region having a second conductivity type;

a source region of the second conductivity type within the body region in the first fin;

a first gate structure arranged to overlap with a first portion of the first fin; and

a first isolation region arranged in the cut between the first fin and the second fin,

wherein the first fin has a top surface, the first isolation region includes a first section and a second section arranged between the first section and the substrate, the first section has a width dimension, and the second section has a width dimension that is less than the width dimension of the first section.

2. The structure of claim 1 wherein the first isolation region has a top surface, and the first gate structure has a terminating surface located on the top surface of the first isolation region.

3. The structure of claim 2 wherein the first fin has a side surface that intersects the top surface of the first fin at a corner, and the terminating surface of the first gate structure is arranged at and above the top surface of the first fin.

4. The structure of claim 1 further comprising:

a second gate structure arranged to overlap a second portion of the first fin, the second gate structure spaced along the first fin from the first gate structure.

5. The structure of claim 4 further comprising:

a second isolation region in the first fin, the second isolation region spaced along the first fin from the first isolation region.

6. The structure of claim 5 wherein the second isolation region is arranged along the first fin between the first gate structure and the second gate structure.

7. The structure of claim 1 further comprising:

a second isolation region in the first fin, the second isolation region spaced along the first fin from the first isolation region.

8. The structure of claim 1 wherein the first isolation region has a top surface, and the top surface of the first fin is coplanar with the top surface of the first isolation region.

9. The structure of claim 1 wherein the first isolation region has a top surface that is arranged below the top surface of the first fin.

10. The structure of claim 1 further comprising:

a contact region of the second conductivity type in the drain region in the second fin,

wherein the first isolation region is arranged between the contact region and the first fin.

11. The structure of claim 1 wherein the first isolation region is arranged at and above the top surface of the substrate.

12. The structure of claim 11 further comprising:

a deep trench isolation region arranged to surround the first fin and the second fin, the deep trench isolation region arranged at least in part below the top surface of the substrate.

13. A method of fabricating a field-effect transistor, the method comprising:

forming a first fin and a second fin each including a top surface, wherein the first fin and the second fin that extend vertically from the respective top surface to a top surface of a substrate, wherein the first fin is separated from the second fin by a cut extending vertically to the top surface of the substrate;

forming a body region that is arranged partially in the substrate and partially in the first fin, the body region having a first conductivity type;

forming a drain region that is arranged partially in the substrate, partially in the first fin, and partially in the second fin, wherein the drain region having has a second conductivity type;

forming a source region of the second conductivity type within the body region in the first fin;

forming a first gate structure arranged to overlap with a first portion of the first fin; and

forming a first isolation region arranged in the cut between the first fin and the second fin,

wherein the first fin has a top surface, the first isolation region includes a first section and a second section arranged between the first section and the substrate, the first section has a width dimension, and the second section has a width dimension that is less than the width dimension of the first section.

14. The method of claim 13 wherein the first isolation region has a top surface, and the first gate structure has a terminating surface located on the top surface of the first isolation region.

15. The method of claim 13 further comprising:

forming a second gate structure arranged to overlap a second portion of the first fin,

wherein the second gate structure is spaced along the first fin from the first gate structure.

16. The method of claim 15 further comprising:

forming a second isolation region in the first fin,

wherein the second isolation region is spaced along the first fin from the first isolation region.

17. The method of claim 16 wherein the second isolation region is arranged along the first fin between the first gate structure and the second gate structure.

18. The method of claim 13 further comprising:

forming a second isolation region in the first fin,

wherein the second isolation region is spaced along the first fin from the first isolation region.

19. The method of claim 13 wherein the first isolation region is arranged at and above the top surface of the substrate.

20. The method of claim 13 further comprising:

forming a deep trench isolation region arranged to surround the first fin and the second fin,

wherein the deep trench isolation region is arranged at least in part below the top surface of the substrate.