Trench isolation having three portions with different materials, and LDMOS FET including same
An IC structure that includes a trench isolation (TI) in a substrate having three portions of different dielectric materials. The portions may also have different widths. The TI may include a lower portion including a first dielectric material and having a first width, a middle portion including the first dielectric material and an outer second dielectric material, and an upper portion including a third dielectric material and having a second width greater than the first width. The first, second and third dielectric materials are different.
1. An integrated circuit (IC) structure, comprising:
a trench isolation (TI) in a substrate, the TI including:
a lower portion including a first dielectric material and having a first width;
a middle portion including the first dielectric material and an outer second dielectric material; and
an upper portion including a third dielectric material and having a second width greater than the first width,
wherein the first, second and third dielectric materials are different,
wherein the third dielectric material contacts the first dielectric layer at a first portion of a material interface and the second dielectric material at a second portion of the material interface, and the third dielectric material has an uppermost surface coplanar with an uppermost surface of the substrate.
2. The IC structure of claim 1 , wherein the outer second dielectric material has a third width between the first width and the second width in size.
3. The IC structure of claim 1 , wherein the third dielectric material is on the first and second dielectric materials.
4. The IC structure of claim 1 , further comprising a gate electrode over the substrate, the gate electrode overlapping the upper portion of the trench isolation, and adjacent to an upper sidewall and above a lower sidewall, of the third dielectric material of the upper portion of the trench isolation.
5. The IC structure of claim 4 , further comprising a first source/drain region and a second source/drain region in the substrate, and wherein the TI and the gate electrode are in between the first source/drain region and the second source/drain region.
6. The IC structure of claim 5 , wherein the first source/drain region is positioned in a first well in the substrate and the second source/drain region is positioned in a second well in the substrate adjacent to the first well.
7. The IC structure of claim 6 , wherein the TI is positioned in the second well, and the first well and the second well define a junction underneath the gate electrode.
8. The IC structure of claim 1 , wherein the substrate includes a semiconductor fin over a base semiconductor layer, and the TI is positioned partially in the semiconductor fin.
9. The IC structure of claim 8 , wherein the lower portion of the TI extends into the base semiconductor layer.
10. A transistor, comprising:
a first source/drain region in a semiconductor substrate and a second source/drain region in the semiconductor substrate;
a trench isolation (TI) in the semiconductor substrate, the TI separating the first source/drain region and the second source/drain region, the TI closer to one of the first source/drain region and the second source/drain region, the TI including:
a lower portion including a first dielectric material and having a first width,
a middle portion including the first dielectric material and an outer second dielectric material, and
an upper portion including a third dielectric material and having a second width greater than the first width, wherein the third dielectric material contacts the first dielectric layer at a first portion of a material interface and the second dielectric material at a second portion of the material interface, and the third dielectric material has an uppermost surface coplanar with an uppermost surface of the semiconductor substrate; and
a gate electrode over the semiconductor substrate, the gate electrode overlapping the upper portion of the TI.
11. The transistor of claim 10 , wherein the outer second dielectric material has a third width between the first width and the second width in size.
12. The transistor of claim 10 , wherein the gate electrode is adjacent to an upper sidewall and above a lower sidewall, of the third dielectric material of the TI.
13. The transistor of claim 10 , wherein the TI and the gate electrode are in between the first source/drain region and the second source/drain region.
14. The transistor of claim 10 , wherein the first source/drain region is positioned in a first well in the semiconductor substrate and the second source/drain region is positioned in a second well in the semiconductor substrate adjacent to the first well, wherein the first well and the second well define a junction underneath the gate electrode and the trench isolation is positioned in the second well.
15. The transistor of claim 10 , wherein the semiconductor substrate includes a semiconductor fin over a base semiconductor layer, and the lower portion extends into the base semiconductor layer.
16. A method comprising:
forming a trench isolation (TI) by:
forming a pair of spaced first trenches into a semiconductor substrate;
forming a middle portion of the TI by filling the pair of spaced first trenches with a first dielectric material, creating a pair of spaced TI sections;
forming a second trench through a remaining portion of the semiconductor substrate between the pair of spaced TI sections and through an inner portion of each of the pair of spaced TI sections into the semiconductor substrate;
forming a lower portion of the TI by filling the second trench with a second dielectric material;
forming a third trench into an upper section of the middle portion of the TI and the semiconductor substrate adjacent the middle portion of the TI; and
forming an upper portion of the TI by filling the third trench with a third dielectric material, wherein the third dielectric material contacts the first dielectric layer at a first portion of a material interface and the second dielectric material at a second portion of the material interface, and the third dielectric material has an uppermost surface coplanar with an uppermost surface of the semiconductor substrate,
wherein the first, second and third dielectric materials are different.
17. The method of claim 16 , wherein the lower portion of the TI has a first width, the middle portion of the TI has a second width, and the upper portion of the TI has a third width, wherein the first, second and third widths are different.
18. The method of claim 16 , wherein the upper portion of the TI contacts the middle portion of the TI and the lower portion of the TI.
19. The method of claim 16 , further comprising:
forming a first well and a second well in the semiconductor substrate, wherein the first and second well include different dopants;
forming a gate electrode over the semiconductor substrate, wherein the gate electrode overlaps the upper portion of the TI and is adjacent to an upper sidewall and above a lower sidewall of the upper portion of the TI, and the first well and the second well form a junction under the gate electrode; and
forming a first source/drain region in the semiconductor substrate and a second source/drain region in the semiconductor substrate,
wherein the TI and the gate electrode are in between the first source/drain region and the second source/drain region, and the TI is in one of the first well and the second well.