IP Library › Granted Patent US 10,295,914
Granted Patent B2
US 10,295,914 · App. 15/358,716 · Granted May 21, 2019

Method and apparatus for fabricating wafer by calculating process correction parameters

Inventor: Boris Habets (Dreseden, DE)
Assignee: Qoniac GmbH
G03F7/70633G05B17/02H01L22/20G05B2219/37224G05B2219/45031
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Quick Facts
Patent No.
US 10,295,914
App. No.
15/358,716
Granted
May 21, 2019
Kind
B2
Abstract

A method of calculating an overlay correction model in a unit for the fabrication of a wafer is disclosed. The method comprises measuring overlay deviations of a subset of first overlay marks and second overlay marks by determining the differences between the subset of first overlay marks generated in the first layer and corresponding ones of the subset of second overlay marks generated in the second layer.

Claims (8)

1. An apparatus for fabrication of a wafer with a structural pattern comprising:

an exposure tool for exposure of the wafer;

an overlay measurement tool for measuring a subset of overlay deviations between lower first overlay marks and second overlay marks in a photoresist layer on the wafer; and

a process correction unit connected to the overlay measurement tool, wherein the process correction unit is configured to:

accept the measured subset of overlay deviations,

calculate from the overlay deviations wafer fine model corrections parameters,

for a plurality of overlay positions estimate overlay residuals from the wafer fine model correction parameters, and calculate a set of field correction parameters for the exposure tool from the overlay residuals, and

provide the wafer fine model correction parameters and the set of field correction parameters to the exposure tool.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 22, 2016
From: HABETS, BORIS
To: QONIAC GMBH
Reel/Frame 040671/0803 →
Continuity (3)
Continuation 13749740 · Jan 25, 2013
Provisional Application 61590665 · Jan 25, 2012
Related Publication 20170075230A1 · Mar 16, 2017
Cited By (1)
US 12,654,315