Back-side deep trench isolation (BDTI) structure for pinned photodiode image sensor
The present disclosure relates to a CMOS image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within a substrate and respectively comprising a photodiode. A back-side deep trench isolation (BDTI) structure is disposed between adjacent pixel regions, extending from a back-side of the substrate to a position within the substrate. The BDTI structure comprises a doped layer lining a sidewall surface of a deep trench and a dielectric fill layer filling a remaining space of the deep trench. By forming the disclosed BDTI structure that functions as a doped well and an isolation structure, the implantation processes from a front-side of the substrate is simplified, and thus the exposure resolution, the full well capacity of the photodiode, and the pinned voltage is improved.
1. A CMOS image sensor, comprising:
a substrate having a front-side and a back-side opposite to the front-side;
a plurality of pixel regions disposed within the substrate and respectively comprising a photodiode configured to convert radiation that enters the substrate from the back-side into an electrical signal; and
a back-side deep trench isolation (BDTI) structure disposed within a deep trench between adjacent pixel regions, extending from the back-side of the substrate to a position within the substrate;
wherein the BDTI structure comprises a doped layer with a first doping type and a dielectric fill layer, the doped layer lining a sidewall surface of the deep trench and the dielectric fill layer filling a remaining space of the deep trench;
wherein the doped layer and the dielectric fill layer of the BDTI structure extend upwardly from the deep trench and laterally disposed along the back-side of the substrate.
2. The CMOS image sensor of claim 1 , further comprising:
a doped isolation layer with the first doping type and comprising a lateral portion and a vertical portion in direct contact with one another, the lateral portion extending along the front-side of the substrate and the vertical portion extending between the adjacent pixel regions from the front-side of the substrate to a position within the substrate.
3. The CMOS image sensor of claim 2 ,
wherein the photodiode comprises a first region with the first doping type and a second region with a second doping type that is different than the first doping type; and
wherein the opposing sides of the first region contact the second region and the doped isolation layer.
4. The CMOS image sensor of claim 2 , wherein the doped isolation layer and the BDTI structure meet within the substrate.
5. The CMOS image sensor of claim 2 , wherein a bottom portion of the BDTI structure is disposed within a recessed top surface of the vertical portion of the doped isolation layer.
6. The CMOS image sensor of claim 1 , the BDTI structure further comprising a high-k dielectric liner disposed between the doped layer and the dielectric fill layer.
7. The CMOS image sensor of claim 1 , further comprising:
a floating diffusion well disposed between the adjacent pixel regions from the front-side of the substrate to a position within the substrate; and
a transfer gate arranged on the front-side of the substrate at a position laterally between the photodiode and the floating diffusion well.
8. The CMOS image sensor of claim 1 , further comprising:
a shallow trench isolation (STI) structure disposed between the adjacent pixel regions from the front-side of the substrate to a position within the substrate;
wherein the STI structure and the BDTI structure are vertically aligned.
9. The CMOS image sensor of claim 8 , further comprising:
a doped isolation layer with the first doping type extending from the front-side of the substrate to a position within the substrate.
10. The CMOS image sensor of claim 9 , wherein the doped isolation layer separates the STI structure from the BDTI structure.
11. The CMOS image sensor of claim 8 , wherein the doped layer of the BDTI structure lands on a planar top surface of the STI structure, while the dielectric fill layer of the BDTI structure extends further down to a concave recess of the STI structure.
12. The CMOS image sensor of claim 1 , further comprising:
a back-end-of-the-line (BEOL) metallization stack arranged on the front-side of the substrate and comprising a plurality of metal interconnect layers arranged within one or more inter-level dielectric layers.
13. A CMOS image sensor, comprising:
a substrate having a front-side and a back-side opposite to the front-side;
a photodiode arranged within the substrate;
a back-side deep trench isolation (BDTI) structure extending from the back-side of the substrate to positions within the substrate on opposing sides of the photodiode; and
a doped isolation layer with a first doping type and comprising a lateral portion and a vertical portion in direct contact with one another, the lateral portion extending along the front-side of the substrate overlying the photodiodes of the pixel regions;
wherein the BDTI structure comprises a doped layer with the first doping type and a dielectric fill layer, the doped layer lining a sidewall surface of a deep trench and the dielectric fill layer filling a remaining space of the deep trench.
14. The CMOS image sensor of claim 13 , wherein the BDTI structure laterally abuts sidewalls of the photodiode.
15. The CMOS image sensor of claim 13 ,
wherein the vertical portion of the doped isolation layer meets the BDTI structure within the substrate.
16. The CMOS image sensor of claim 15 , further comprising:
a shallow trench isolation (STI) structure extending from the front-side of the substrate to a position within the doped isolation layer;
wherein the STI structure and the BDTI structure are vertically aligned.
17. The CMOS image sensor of claim 13 , the BDTI structure further comprising:
a high-k dielectric liner disposed between the doped layer and the dielectric fill layer.
18. The CMOS image sensor of claim 13 , wherein a bottom portion of the BDTI structure is disposed within a recessed top surface of the vertical portion of the doped isolation layer.
19. The CMOS image sensor of claim 13 , wherein the vertical portion extends between the adjacent pixel regions from the front-side of the substrate to a position within the substrate deeper than that of the lateral portion.
20. A method of forming an image sensor, comprising:
forming doping layers corresponding to photodiodes of a plurality of pixel regions from a front-side of a substrate;
forming a doped isolation layer from the front-side of the substrate by implanting a dopant species into the substrate through a plurality of implanting processes, the doped isolation layer comprising a vertical portion between adjacent pixel regions;
forming a shallow trench isolation (STI) structure between the adjacent pixel regions from the front-side of the substrate to a position within the substrate;
rotating the substrate and etching from a back-side of the substrate to form a deep trench between adjacent pixel regions and extending into the substrate, wherein the back-side of the substrate opposes the front-side of the substrate; and
filling the deep trench with a doped layer and a dielectric fill layer a dielectric layer to form a back-side deep trench isolation (BDTI) structure that are disposed between the adjacent pixel regions and separate photodiodes of the adjacent pixel regions;
wherein the doped isolation layer separates the STI structure from the BDTI structure.