High voltage transistor using buried insulating layer as gate dielectric
A high voltage transistor may be formed on the basis of well-established CMOS techniques by using a buried insulating material of an SOI architecture as gate dielectric material, while the gate electrode material may be provided in the form of a doped semiconductor region positioned below the buried insulating layer. The high voltage transistor may be formed with high process compatibility on the basis of a process flow for forming sophisticated fully depleted SOI transistors, wherein, in some illustrative embodiments, the high voltage transistor may also be provided as a fully depleted transistor configuration.
1. A semiconductor device, comprising:
a channel region in a semiconductor layer;
drain and source regions positioned on said semiconductor layer so as to laterally connect to said channel region;
a buried insulating layer including a portion positioned below said channel region;
a doped region positioned below said buried insulating layer and connected to a gate contact region, said portion of said buried insulating layer and said doped region forming a gate electrode structure of a transistor element; and
an interlayer dielectric material laterally extending continuously between said drain region and said source region across an entire height of said drain region and said source region.
2. The semiconductor device of claim 1 , wherein a thickness of said buried insulating layer is 30 nm or less.
3. The semiconductor device of claim 1 , wherein a thickness of said semiconductor layer is 15 nm or less.
4. The semiconductor device of claim 1 , wherein said doped region is delineated in a transistor length direction by a trench isolation structure.
5. The semiconductor device of claim 1 , wherein said doped region is embedded in a substrate material and is, in a transistor length direction, laterally offset from a trench isolation structure.
6. The semiconductor device of claim 1 , further comprising a fully depleted transistor element including a gate electrode structure formed above said buried insulating layer, wherein said fully depleted transistor element has an operating voltage of 2V or less.
7. The semiconductor device of claim 6 , wherein said gate electrode structure of said low power transistor element comprises a high-k dielectric material.
8. The semiconductor device of claim 1 , wherein said drain and source regions are formed on said semiconductor layer as raised drain and source regions.
9. A transistor element, comprising:
a channel region positioned between a drain region and a source region;
a portion of a buried insulating layer positioned below at least said channel region;
a doped semiconductor region positioned below said portion of said buried insulating layer and connected to a control terminal, said portion of said buried insulating layer and said doped semiconductor region forming a gate electrode structure; and
an interlayer dielectric material laterally extending continuously between said drain region and said source region across an entire height of said drain region and said source region.
10. The transistor element of claim 9 , wherein a physical thickness of said channel region is 15 nm or less.
11. The transistor element of claim 9 , wherein said drain and source regions are raised semiconductor regions.
12. The transistor element of claim 9 , wherein said doped semiconductor region is laterally delineated in a transistor length direction by a trench isolation structure.
13. The transistor element of claim 9 , wherein said doped semiconductor region is laterally offset from said drain and source regions in a transistor length direction.
14. The transistor element of claim 9 , wherein a thickness of said portion of said buried insulating layer is 10 nm and greater.
15. A method, comprising:
forming a gate electrode structure of a transistor element by doping a portion of a substrate material of a semiconductor substrate below a portion of a buried insulating layer;
forming a drain region and a source region on a semiconductor layer formed on said buried insulating layer; and
forming an interlayer dielectric material laterally extending continuously between said drain region and said source region across an entire height of said drain region and said source region.
16. The method of claim 15 , wherein doping said portion of said substrate material comprises forming said portion so as to be laterally delineated in a transistor length direction by a trench isolation structure.
17. The method of claim 15 , wherein doping said portion of said substrate material comprises forming said portion so as to be embedded in said substrate material and laterally offset in a transistor length direction from a trench isolation structure.
18. The method of claim 15 , further comprising forming at least one further transistor element with second drain and source regions in said semiconductor layer and with a gate electrode structure formed on said semiconductor layer and positioned laterally between said second drain and source regions.
19. The method of claim 15 , wherein forming said drain region and said source region comprises:
forming a spacer layer above said semiconductor layer;
forming a mask above said spacer layer;
patterning said spacer layer in the presence of said mask; and
forming said drain region and said source region in the presence of said patterned spacer layer.
20. The method of claim 19 , further comprising:
forming said spacer layer above a gate electrode structure of a further transistor; and
patterning said spacer layer to define spacers adjacent said gate electrode structure.