Dense redistribution layers in semiconductor packages and methods of forming the same

1. A method comprising:

forming a patterned first photo resist over a seed layer, wherein a first opening in the patterned first photo resist exposes the seed layer;

plating a first conductive material in the first opening on the seed layer;

removing the patterned first photo resist;

after removing the patterned first photo resist, forming a patterned second photo resist over and along sidewalls of the first conductive material, wherein a second opening in the patterned second photo resist exposes a portion of an upper surface and a sidewall of the first conductive material, wherein the second opening does not expose the seed layer in a cross-sectional view;

plating a second conductive material in the second opening on the first conductive material;

removing the patterned second photo resist;

after removing the patterned second photo resist, removing exposed portions of the seed layer; and

depositing a dielectric layer around the first conductive material and the second conductive material.

2. The method of claim 1 further comprising planarizing the dielectric layer so that a top surface of the dielectric layer is substantially level with a top surface of the second conductive material.

3. The method of claim 1 , wherein a photosensitive material of the patterned second photo resist is disposed between a bottom surface of the second conductive material and the seed layer.

4. The method of claim 1 further comprising depositing the seed layer over an integrated circuit die and on an encapsulant encapsulating the integrated circuit die.

5. The method of claim 1 further comprising:

depositing the seed layer over a carrier substrate; and

after depositing the dielectric layer, bonding an integrated circuit die over the dielectric layer using a flip chip bonding process.

6. The method of claim 5 further comprising encapsulating the integrated circuit die, wherein encapsulating the integrated circuit die comprises dispensing an encapsulant between a bottom surface of the integrated circuit die and the dielectric layer.

7. The method of claim 1 , wherein the dielectric layer comprises a photosensitive polymer, and wherein the patterned second photo resist supports a higher resolution lithography process than the photosensitive polymer.

8. The method of claim 1 , wherein the dielectric layer comprises an oxide.

9. The method of claim 1 , wherein the dielectric layer contacts a sidewall of the first conductive material directly below the second conductive material.

10. A method comprising:

encapsulating an integrated circuit die in an encapsulant;

depositing a first photo resist over the encapsulant and the integrated circuit die;

patterning a first opening in the first photo resist to expose a first conductive material;

plating a conductive via in the first opening, wherein the conductive via is electrically connected to the integrated circuit die, wherein a bottom surface of the conductive via contacts the first photo resist;

removing the first photo resist;

after removing the first photo resist, depositing a first polymer layer around the conductive via, wherein the first polymer layer and the first photo resist comprise different materials, wherein depositing the first polymer layer comprises depositing a portion of the first polymer layer directly under the bottom surface of the conductive via; and

planarizing the first polymer layer so that a top surface of the first polymer layer and a top surface of the conductive via are substantially level.

11. The method of claim 10 , wherein the first conductive material is a conductive line, wherein depositing the first polymer layer further comprises depositing the first polymer layer along sidewalls of the conductive line.

12. The method of claim 11 further comprising:

depositing a second photo resist over the integrated circuit die and the encapsulant;

patterning a second opening in the second photo resist;

plating the conductive line in the second opening, wherein the conductive line is electrically connected to the integrated circuit die; and

removing the second photo resist, wherein the first photo resist is deposited after the second photo resist is removed.

13. The method of claim 10 , wherein the first polymer layer contacts a sidewall of the first conductive material directly below the conductive via.

14. The method of claim 10 , wherein the first opening exposes a top surface and a sidewall of the first conductive material, wherein the first opening does not extend to a bottom of the first conductive material.

15. A method comprising:

encapsulating an integrated circuit die in an encapsulant;

depositing a first mask over the encapsulant and the integrated circuit die, wherein the first mask is a single material layer;

patterning a first opening in the first mask to expose a first conductive element;

forming a conductive via in the first opening, wherein the conductive via is electrically connected to the integrated circuit die, wherein a bottom surface of the conductive via is over the first mask;

removing the first mask, wherein after removing the first mask, a top surface, the bottom surface, a first sidewall surface extending between the top surface and the bottom surface, and a second sidewall surface extending between the top surface and the bottom surface of the conductive via are at least partially exposed;

depositing a first insulating layer around the conductive via, wherein the first insulating layer and the first mask comprise different layers; and

planarizing the first insulating layer to expose an upper surface of the conductive via.

16. The method of claim 15 , wherein the first mask comprises a photo resist layer.

17. The method of claim 15 , wherein the first insulating layer comprises a polymer.

18. The method of claim 15 , wherein patterning the first opening comprises exposing a sidewall of the first conductive element.

19. The method of claim 15 , wherein the first insulating layer comprises an oxide.

20. The method of claim 15 , wherein the first insulating layer contacts a surface of the first conductive element directly below the conductive via.