Vertical transistors with sidewall gate air gaps and methods therefor
A method is provided that includes forming a first vertically-oriented transistor above a substrate, the first vertically-oriented transistor comprising a first sidewall gate disposed in a first direction, forming a second vertically-oriented transistor above the substrate, the second vertically-oriented transistor including a second sidewall gate disposed in the first direction, and forming an air gap chamber above the substrate disposed between the first sidewall gate and the second sidewall gate, and extending in the first direction, the air gap chamber including an air gap.
1. A monolithic three-dimensional memory array comprising:
a first vertically-oriented bit line select transistor disposed above a substrate, the first vertically-oriented bit line select transistor comprising a first sidewall gate;
a second vertically-oriented bit line select transistor disposed above the substrate, the second vertically-oriented bit line select transistor comprising a second sidewall gate; and
an air gap chamber disposed above the substrate between the first vertically-oriented bit line select transistor and the second vertically-oriented bit line select transistor, the air gap chamber comprising a liner substantially enclosing an air gap, the liner formed on a sidewall of the first sidewall gate and a sidewall of the second sidewall gate,
wherein the liner comprises a first section adjacent the first sidewall gate, and a second section adjacent the second sidewall gate, and the first section and the second section bend or pitch towards one another.
2. The monolithic three-dimensional memory array of claim 1 , wherein the liner comprises a material having a tensile stress.
3. The monolithic three-dimensional memory array of claim 1 , wherein monolithic three-dimensional memory array comprises a vertical strip of non-volatile memory material comprising any of a reversible resistance-switching material, a phase change material, and a charge trapping layer.