Multi-state phase change memory device with vertical cross-point structure

1. An apparatus, comprising:

a three-dimensional array of non-volatile memory cells formed over a substrate, comprising:

a plurality of layers of word lines, each of the layers of word lines running horizontally over the substrate, the layers separated in a vertical direction by dielectric layers;

a plurality of bit lines running vertically with respect to the substrate; and

a plurality of memory cells each connected between a corresponding one of the word lines and a corresponding one of the bit lines, each of the memory cells comprising:

a phase change memory material configured to provide a first current path between the corresponding word line and the corresponding bit line for the memory cell, the phase change memory material having a first resistivity in a first phase and a second resistivity in a second phase, the first resistivity being higher than the second resistivity; and

an intermediate resistance material adjacent to the phase change memory material and configured to provide second current path in parallel with the first current path between the memory cell's corresponding word line and bit line, the intermediate resistance material having a resistivity between the first and second resistivities; and

one or more control circuits connected to the three-dimensional array of non-volatile memory cells, the control circuits configured to program multi-state data into the memory cells and read multi-state data from the memory cells.

2. The apparatus of claim 1 , wherein the one or more control circuits are configured to program a selected memory cell from an erased state to a target state by applying a current pulse across the selected memory cell high enough to raise at least a portion of the phase change memory material of the selected memory cell above melting temperature thereof across the selected memory cell, an amplitude of the current pulse dependent upon the target state.

3. The apparatus of claim 2 , wherein the one or more control circuits comprise:

programming circuitry including a current mirror having a first leg connectable to the selected memory cell and a second leg connectable to a plurality of programming current levels.

4. The apparatus of claim 2 , wherein the one or more control circuits are further configured to program the selected memory cell from an erased state to a target state by performing a verify operation subsequent to applying the current pulse and, based on the verify operation, applying an additional current pulse across the selected memory cell.

5. The apparatus of claim 1 , wherein the one or more control circuits are configured to program a selected memory cell from an erased state to a target state by applying a current pulse across the selected memory cell high enough to raise at least a portion of the phase change memory material of the selected memory cell above melting temperature thereof across the memory cell, a duration of the current pulse dependent upon the target state.

6. The apparatus of claim 1 , wherein the one or more control circuits are configured to erase a selected memory cell from an erased state to a target state by applying a current across the selected memory cell sufficient to raise a temperature of phase change memory material of the selected memory cell above a crystallization temperature, but not above a melt temperature, of the phase change memory material.

7. The apparatus of claim 1 , wherein the one or more control circuits are configured to read a selected memory cell by comparing a current flowing though selected the memory cell with a reference current.

8. The apparatus of claim 7 , wherein the one or more control circuits are configured to generate the current flowing through the selected memory cell in response to one of a plurality of read voltage levels.

9. The apparatus of claim 8 , wherein the one or more control circuits comprise:

read circuitry including a current mirror having a first leg connectable to the selected memory cell to apply a current level thereto dependent on the one of the read voltage levels and a second leg to compare applied current level to a reference current.

10. The apparatus of claim 1 , wherein each of the memory cells further comprise:

a selector switch connected between parallel first and second current paths and the corresponding bit line.

11. The apparatus of claim 1 , wherein the phase change memory material and the intermediate resistance material of each of the memory cells are confined within a pore structure in the dielectric layers.

12. The apparatus of claim 1 , wherein the phase change memory material includes a chalcogenide material.

13. The apparatus of claim 1 , wherein the intermediate resistance material includes a metal-nitride.

14. A non-volatile memory device, comprising:

a memory array having a three-dimensional, vertical cross-point architecture of multi-state memory cells disposed horizontally between word lines and bit lines, each of the memory cells comprising a phase change memory material confined within a pocket lined with a surfactant within a dielectric material; and

one or more control circuits, including read circuitry configured to read a read selected multi-state memory cell by comparing a current flowing though the read selected memory cell with a reference current and write circuitry configured to program a write selected memory cell from an erased state to a one of a plurality of target states by applying a current pulse across the write selected memory cell high enough to raise at least a portion of the phase change memory material of the write selected memory cell above a melting temperature thereof.

15. The non-volatile memory device of claim 14 , the read circuitry including a current mirror having a first leg connectable to the read selected memory cell to apply a current level thereto dependent on the one of a plurality of read voltage levels and a second leg to compare applied current level to a reference current.

16. The non-volatile memory device of claim 14 , wherein an amplitude of the current pulse dependent upon the target state.

17. The non-volatile memory device of claim 16 , the write circuitry including a current mirror having a first leg connectable to the write selected memory cell and a second leg connectable to a plurality of programming current levels.

18. The non-volatile memory device of claim 14 , the control circuits further comprising erase circuitry configured to erase an erase selected memory cell from any of the plurality of target states to the erased state by applying a current across the erase selected memory cell sufficient to raise a temperature of phase change memory material of the erase selected memory cell above a crystallization temperature, but not above the melting temperature, of the phase change memory material.

19. The non-volatile memory of claim 14 , wherein the phase change memory material includes a chalcogenide material.

20. A non-volatile memory device, comprising:

a memory array, comprising:

a plurality of word lines running in a horizontal direction;

a plurality of bit lines running in a vertical direction; and

a plurality of multi-state memory cells each connected between a corresponding word line and a corresponding bit line, each of the memory cells comprising:

a phase change memory material having a first resistivity in a first phase and a second resistivity in a second phase, the first resistivity being higher than the second resistivity; and

means for providing an additional current path adjacent to the phase change memory material having a resistivity higher than the second resistivity and lower than the first resistivity; and

means for reading a data state stored in each of the multi-state memory cells; and

means for writing one of a plurality of data states to each of multi-state memory cells by applying a current pulse having an amplitude dependent upon the data state to which the multi-state memory cell is to be programmed.