Replacement body FinFET for improved junction profile with gate self-aligned junctions
After forming an epitaxial semiconductor layer on portions of a semiconductor located on opposite sides of a sacrificial gate structure, dopants from the epitaxial semiconductor layer are diffused into the semiconductor fin to form a dopant-containing semiconductor fin. A sacrificial gate stack is removed to provide a gate cavity that exposes a portion of the dopant-containing semiconductor fin. The exposed portion of the dopant-containing semiconductor fin is removed to provide an opening underneath the gate cavity. A channel which is undoped or less doped than remaining portions of the dopant-containing semiconductor fin is epitaxially grown at least from the sidewalls of the remaining portions of the dopant-containing semiconductor fin. Abrupt junctions are thus formed between the channel region and the remaining portions of the dopant-containing semiconductor fin.
1. A semiconductor structure comprising:
a source region and a drain region spaced apart from each other and located on a substrate;
a template region located on the substrate and laterally abutted by the source region and the drain region;
a channel region wrapping around the template region and laterally abutted by the source region and the drain region; and
a gate stack wrapping around the channel region, wherein sidewalls of the gate stack are vertically aligned with end walls of the channel region and end walls of the template region.
2. The semiconductor structure of claim 1 , wherein each of the template region, the source region and the drain region comprises a first semiconductor material, and the channel region comprises a second semiconductor material.
3. The semiconductor structure of claim 2 , wherein the second semiconductor material is the same as the first semiconductor material.
4. The semiconductor structure of claim 2 , wherein the second semiconductor material is different from the first semiconductor material.
5. The semiconductor structure of claim 4 , wherein each of the template region, the source region and the drain region comprises Si, and the channel region comprises germanium.
6. The semiconductor structure of claim 1 , wherein each of the template region, the source region and the drain region comprises first dopants of a first conductivity type.
7. The semiconductor structure of claim 6 , wherein the template region has a first dopant concentration, and each of the source region and the drain region has a second dopant concentration that is greater than the first dopant concentration.
8. The semiconductor structure of claim 7 , wherein the first dopant concentration is below 1×10 19 atoms/cm 3 , and the second dopant concentration is above 1×10 19 atoms/cm 3 .
9. The semiconductor structure of claim 6 , wherein the template region has a graded dopant concentration such that the dopant concentration decreases gradually towards a center of the template region.
10. The semiconductor structure of claim 6 , wherein the channel region is intrinsic.
11. The semiconductor structure of claim 6 , wherein the channel region comprises second dopants of a second conductivity type opposite to the first conductivity type.
12. The semiconductor structure of claim 7 , further comprising a raised source region present on the source region and a raised region present on the drain region, wherein each of the raise source region and the raised drain region comprises the first dopants of the first conductivity type.
13. The semiconductor structure of claim 12 , wherein each of the raised source region and the raised drain region has a third dopant concentration greater than the second dopant concentration of each of the source region and the drain region.
14. The semiconductor structure of claim 12 , wherein each of the raised source region and the raised drain region comprises a third semiconductor material the same as, or different from, the first semiconductor material.
15. The semiconductor structure of claim 14 , wherein each of the raised source region and the raised drain region comprises silicon, silicon germanium, germanium, silicon-carbon or a compound semiconductor material.
16. The semiconductor structure of claim 1 , wherein the top surface of the template region is located below a top surface of each of the source region and the drain region.
17. The semiconductor structure of claim 16 , wherein the top surface of the channel region is coplanar with the top surface of each of the source region and the drain region.
18. The semiconductor structure of claim 1 , wherein heights of sidewalls of the template region are offset from that of sidewalls of the source region and the drain region.
19. The semiconductor structure of claim 18 , wherein sidewalls of the channel region and the sidewalls of each of the source region and the drain region are located within same vertical planes.
20. The semiconductor structure of claim 1 , further comprising a gate spacer present on sidewalls of the gate stack, wherein the gate spacer vertically contacts a portion of each of the source region and the drain region adjoined to the channel region.