Semiconductor package
A semiconductor package includes a first semiconductor chip including a first through-silicon via (TSV), a second semiconductor chip stacked on the first semiconductor chip and including a second TSV, and a non-conductive film formed between the first semiconductor chip and the second semiconductor chip. The non-conductive film includes two layers having different viscosities.
1. A semiconductor package comprising:
a first semiconductor chip comprising a first through-silicon via (TSV);
a second semiconductor chip stacked on the first semiconductor chip, the second semiconductor chip comprising a second TSV;
a connection member between the first semiconductor chip and the second semiconductor chip, and electrically connecting the first TSV and the second TSV; and
a non-conductive film between the first semiconductor chip and the second semiconductor chip, and on a side surface of the connection member, the non-conductive film comprising a first layer and a second layer that are vertically stacked, and the first layer directly contacting a top surface of the first semiconductor chip and the second layer directly contacting a bottom surface of the second semiconductor chip,
wherein the first layer extends onto a side surface of the second layer,
wherein the first layer and the second layer have different viscosities, respectively, and
wherein the viscosity of the second layer is higher than that of the first layer.
2. The semiconductor package of claim 1 , wherein a thickness of the non-conductive film has a range of 10 micrometers (μm) to 20 μm.
3. The semiconductor package of claim 1 , wherein a thickness of the first layer measured at a center portion of the first layer is less than a thickness of the second layer measured at a center portion of the second layer.
4. The semiconductor package of claim 1 , wherein the first semiconductor chip and the second semiconductor chip are covered by an epoxy mold compound (EMC), and a side surface of the first layer contacts the EMC.
5. The semiconductor package of claim 4 , wherein the side surface of the second layer does not contact the EMC.
6. The semiconductor package of claim 1 ,
wherein the first layer and the second layer comprise first ceramic fillers and second ceramic fillers, respectively, and
wherein an average diameter of the first ceramic fillers is greater than an average diameter of the second ceramic fillers.
7. The semiconductor package of claim 1 , wherein a portion of a side surface of the first semiconductor chip is free of the first layer.
8. The semiconductor package of claim 1 , wherein a portion of a side surface of the second semiconductor chip is free of the first layer.
9. A semiconductor package comprising:
a first semiconductor chip comprising a first through-silicon via (TSV);
a second semiconductor chip stacked on the first semiconductor chip, the second semiconductor chip comprising a second TSV;
a connection member between the first semiconductor chip and the second semiconductor chip, and electrically connecting the first TSV and the second TSV; and
a non-conductive film between the first semiconductor chip and the second semiconductor chip, and on a side surface of the connection member, the non-conductive film comprising a first layer and a second layer that are vertically stacked, and the first layer directly contacting a top surface of the first semiconductor chip and the second layer directly contacting a bottom surface of the second semiconductor chip,
wherein the first layer extends onto a side surface of the second layer,
wherein the first layer further extends onto a first portion of a side surface of the second semiconductor chip, and
wherein a second portion of the side surface of the second semiconductor chip is free of the first layer.
10. The semiconductor package of claim 9 ,
wherein the first layer further extends onto a first portion of a side surface of the first semiconductor chip, and
wherein a second portion of the side surface of the first semiconductor chip is free of the first layer.
11. The semiconductor package of claim 9 , wherein a horizontal width of a first portion of the first layer on the side surface of the second layer is thinner than a vertical thickness of a second portion of the first layer between the top surface of the first semiconductor chip and a bottom surface of the second layer.
12. A semiconductor package comprising:
a base substrate;
a first semiconductor chip comprising a first through-silicon via (TSV);
a second semiconductor chip stacked on the first semiconductor chip, the second semiconductor chip comprising a second TSV;
a first connection member between the first semiconductor chip and the second semiconductor chip, and electrically connecting the first TSV and the second TSV;
a second connection member between the base substrate and the first semiconductor chip, and electrically connecting a pad on the base substrate and the first TSV;
a first non-conductive film between the first semiconductor chip and the second semiconductor chip and on a side surface of the first connection member, the first non-conductive film comprising a first layer and a second layer that are vertically stacked, and the first layer directly contacting a top surface of the first semiconductor chip and the second layer directly contacting a bottom surface of the second semiconductor chip; and
a second non-conductive film between the base substrate and the first semiconductor chip and on a side surface of the second connection member, the second non-conductive film comprising a third layer and a fourth layer that are vertically stacked, and the third layer directly contacting a top surface of the base substrate and the fourth layer directly contacting a bottom surface of the first semiconductor chip,
wherein the first layer extends onto a side surface of the second layer, and the third layer extends onto a side surface of the fourth layer,
wherein the third layer and the fourth layer comprise third ceramic fillers and fourth ceramic fillers, respectively, and
wherein an average diameter of the third ceramic fillers is greater than an average diameter of the fourth ceramic fillers.
13. The semiconductor package of claim 12 ,
wherein the third layer further extends onto a first portion of a side surface of the first semiconductor chip, and
wherein a second portion of the side surface of the first semiconductor chip is free of the third layer.
14. The semiconductor package of claim 12 , wherein a width of the base substrate is greater than that of the first semiconductor chip.
15. The semiconductor package of claim 12 , wherein the third layer and the fourth layer have different viscosities, respectively.
16. The semiconductor package of claim 15 , wherein the viscosity of the fourth layer is higher than that of the third layer.
17. The semiconductor package of claim 12 , wherein a thickness of the second non-conductive film has a range of 10 micrometers (μm) to 20 μm.
18. The semiconductor package of claim 12 , wherein a thickness of the third layer measured at a center portion of the third layer is less than a thickness of the fourth layer measured at a center portion of the fourth layer.
19. The semiconductor package of claim 12 , wherein the first semiconductor chip is covered by an epoxy mold compound (EMC), and a side surface of the third layer contacts the EMC.
20. The semiconductor package of claim 19 , wherein the side surface of the fourth layer does not contact the EMC.