IP Library Granted Patent US 10,446,559
Granted Patent B2
US 10,446,559 · App. 16/053,748 · Granted Oct 15, 2019

Method of fabricating DRAM

Inventors: Tzu-Chin Wu (Chiayi County, TW); Chao-An Liu (Taipei, TW); Ching-Hsiang Chang (Tainan, TW); Yi-Wei Chen (Taichung, TW)
Assignees: UNITED MICROELECTRONICS CORP.; Fujian Jinhua Integrated Circuit Co., Ltd.
H01L27/10891H01L21/0217H01L21/02164H01L21/02211H01L21/02271H01L21/0332H01L21/3081H01L21/3086H01L21/30604H01L27/10823H01L27/10855H01L27/10876H01L21/0273
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,446,559
App. No.
16/053,748
Granted
Oct 15, 2019
Kind
B2
Abstract

A method of fabricating a DRAM includes providing a substrate. Later, a first mask layer is formed to cover the substrate. The first mask layer includes a hydrogen-containing silicon nitride layer and a silicon oxide layer. The hydrogen-containing silicon nitride layer has the chemical formula: Si x N y H z , wherein x is between 4 and 8, y is between 3.5 and 9.5, and z equals 1. After that, the first mask layer is patterned to form a first patterned mask layer. Next, the substrate is etched by taking the first patterned mask layer as a mask to form a word line trench. Subsequently, the first patterned mask layer is removed entirely. Finally, a word line is formed in the word line trench.

Claims (21)

1. A method of fabricating a DRAM, comprising:

providing a substrate; and

forming a first mask layer, wherein the steps of forming the first mask layer comprise:

forming a hydrogen-containing silicon nitride layer to cover the substrate, and forming a silicon oxide layer to cover and contact the hydrogen-containing silicon nitride layer, wherein the hydrogen-containing silicon nitride layer has the chemical formula: Si x N y H z , wherein x is between 4 and 8, y is between 3.5 and 9.5, and z equals 1;

patterning the first mask layer to form a first patterned mask layer;

etching the substrate by taking the first patterned mask layer as a first mask to form a word line trench;

removing the first patterned mask layer entirely; and

forming a word line in the word line trench.

2. The method of fabricating a DRAM of claim 1 , wherein the substrate comprises a semiconductor substrate and a second mask layer covering the semiconductor substrate.

3. The method of fabricating a DRAM of claim 2 , wherein the fabricating steps of the word line comprise:

etching the second mask layer to forma second patterned mask layer by taking the first patterned mask layer as a second mask;

removing the first patterned mask layer;

etching the semiconductor substrate to form the word line trench by taking the second patterned mask layer as a third mask; and

removing the second patterned mask layer.

4. The method of fabricating a DRAM of claim 1 , further comprising:

forming a doping region in the substrate before forming the first mask layer;

forming a capacitor plug to contact the doping region after forming the word line; and

forming a capacitor on the substrate to complete the DRAM after forming the word line, wherein the capacitor electrically connects to the word line through the doping region and the capacitor plug.

5. The method of fabricating a DRAM of claim 1 , wherein the hydrogen-containing silicon nitride layer is formed by a deposition process, and the deposition process comprises:

forming the hydrogen-containing silicon nitride layer by using silane and ammonia as precursors, wherein a flow rate of the silane is between 22.5 and 27.5 SCCM, and a flow rate of the ammonia is between 45 and 55 SCCM.

6. The method of fabricating a DRAM of claim 5 , wherein an operation temperature of the deposition process is between 360 and 440 degrees Celsius, an operation pressure is between 5.4 and 6.6 torrs, and an operation power is between 72 and 88 watts.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2018
From: WU, TZU-CHIN; LIU, CHAO-AN; CHANG, CHING-HSIANG; CHEN, YI-WEI
To: UNITED MICROELECTRONICS CORP.; FUJIAN JINHUA INTEGRATED CIRCUIT CO., LTD.
Reel/Frame 046544/0988 →
Priority Claims (1)
CN 2017 1 0933813 · Oct 10, 2017 · national
Continuity (1)
Related Publication 20190109139A1 · Apr 11, 2019
Cited By (2)
US 12,349,340 US 12,652,797