IP Library Granted Patent US 12,652,797
Granted Patent B2
US 12,652,797 · App. 18/754,195 · Granted Jun 9, 2026

Method of forming semiconductor memory device

Inventors: Yi-Wei Chen (Taichung City, TW); Hsu-Yang Wang (Tainan City, TW); Chun-Chieh Chiu (Keelung City, TW); Shih-Fang Tzou (Tainan City, TW)
Assignees: UNITED MICROELECTRONICS CORP; Fujian Jinhua Integrated Circuit Co., Ltd.
H10B12/485H10B12/053H10B12/482H10W20/0698H10W20/081H10W20/082H10W20/083H10W20/092
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Quick Facts
Patent No.
US 12,652,797
App. No.
18/754,195
Granted
Jun 9, 2026
Kind
B2
Abstract

A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.

Claims (22)

1 . A method of forming a semiconductor memory device, comprising:

providing a substrate;

forming a plurality of gates in the substrate, extending along a first direction;

forming an insulating layer, on the substrate, covering the gates;

forming a plurality of bit lines on the insulating layer, extending in a second direction being perpendicular to the first direction; and

forming a plug under each of the bit lines, between two adjacent ones of the gates, the plug physically contacting each of the bit lines;

wherein forming the plug and the bit lines further comprising:

forming a semiconductor layer on the insulating layer;

forming a protection layer on the semiconductor layer;

forming a plug hole in the protection layer and the semiconductor layer;

forming a conductive layer on the semiconductor layer to fill in the plug hole and to have a lower sunken top surface above the plug hole;

performing a mechanical polishing process to remove the conductive layer having the lower sunken top surface, the protection layer and peripheral taper protrusion portions of the plug, to form the plug having a planar top surface flush with a top surface of the semiconductor layer, wherein a portion of the semiconductor layer around the plug is in direct contact with a sidewall of the plug; and

forming a stacked structure on the planar top surface of the plug and on the top surface of the semiconductor layer, to form the bit lines.

2 . The method of forming a semiconductor memory device according to claim 1 , wherein the conductive layer is formed through performing a chemical vapor deposition, and the mechanical polishing process is performed after performing the chemical vapor deposition.

3 . The method of forming a semiconductor memory device according to claim 2 , further comprising:

performing an etching back process after the chemical vapor deposition, to remove the conductive layer on the semiconductor layer till a peripheral top surface of the conductive layer is lever with a top surface of the protection layer, and a center top surface is sunken within the plug hole, and the mechanical polishing process is performed after performing the etching back process.

4 . The method of forming a semiconductor memory device according to claim 2 , wherein the peripheral top surface of the conductive layer and the protection layer are simultaneously removed while performing the mechanical polishing process.

5 . The method of forming a semiconductor memory device according to claim 1 , wherein materials of the semiconductor layer and the conductive layer are different from each other.

6 . The method of forming a semiconductor memory device according to claim 4 , wherein the conductive layer comprises silicon phosphate.

7 . The method of forming a semiconductor memory device according to claim 1 , wherein a thickness of the semiconductor layer is greater than the insulating layer.

8 . The method of forming a semiconductor memory device according to claim 7 , wherein the thickness of the semiconductor layer is from 40 nm to 50 nm.

9 . The method of forming a semiconductor memory device according to claim 1 , wherein the insulating layer comprises an oxide-nitride-oxide (ONO) structure.

Priority Claims (1)
CN 201810425155.8 · May 7, 2018 · national
Continuity (4)
Continuation 18199346 · May 18, 2023
Division 17161685 · Jan 29, 2021
Division 16001949 · Jun 7, 2018
Related Publication 20240349493A1 · Oct 17, 2024
References Cited (41)
US 9082647B2 · Jang et al. · 2015 [cited by applicant]
US 9082755B2 · Kim · 2015 [cited by applicant]
US 9142536B2 · Kim · 2015 [cited by applicant]
US 9165934B2 · Choi et al. · 2015 [cited by applicant]
US 9178051B2 · Yu · 2015 [cited by applicant]
US 9230853B2 · Yu et al. · 2016 [cited by applicant]
US 9287395B2 · Jeong · 2016 [cited by examiner]
US 10446559B2 · Wu · 2019 [cited by applicant]
US 10475799B2 · Chen · 2019 [cited by applicant]
US 10770464B2 · Liu · 2020 [cited by applicant]
US 10818664B2 · Chang · 2020 [cited by applicant]
US 11508614B2 · Feng · 2022 [cited by applicant]
US 20050142845A1 · Lee · 2005 [cited by examiner]
US 20100117132A1 · Chou · 2010 [cited by examiner]
US 20110086503A1 · Lim · 2011 [cited by examiner]
US 20110260288A1 · Sukekawa · 2011 [cited by examiner]
US 20120012911A1 · Jeong · 2012 [cited by examiner]
US 20120132970A1 · Park · 2012 [cited by examiner]
US 20120193796A1 · Lin et al. · 2012 [cited by applicant]
US 20120217559A1 · Kim · 2012 [cited by applicant]
US 20130264638A1 · Jang · 2013 [cited by examiner]
US 20140308794A1 · Lee · 2014 [cited by applicant]
US 20150061042A1 · Cheng · 2015 [cited by examiner]
US 20150303201A1 · Lee et al. · 2015 [cited by applicant]
US 20160072051A1 · Iwayama · 2016 [cited by examiner]
US 20160181198A1 · Kim · 2016 [cited by examiner]
US 20160247901A1 · Yuan et al. · 2016 [cited by applicant]
US 20160268262A1 · Yoo · 2016 [cited by applicant]
US 20170062339A1 · Hsu · 2017 [cited by examiner]
US 20170117372A1 · Li · 2017 [cited by examiner]
US 20200152649A1 · Chern · 2020 [cited by examiner]
US 20230020696A1 · Chang · 2023 [cited by examiner]
CN 102237393A · 2011 [cited by applicant]
CN 102339829A · 2012 [cited by applicant]
CN 104103577A · 2014 [cited by examiner]
CN 108257919A · 2018 [cited by examiner]
KR 20010057666A · 2001 [cited by examiner]
KR 101205053B1 · 2012 [cited by examiner]
KR 101205118B1 · 2012 [cited by examiner]
KR 101662280B1 · 2016 [cited by examiner]
Liu, the specification, including the claims, and drawings in the U.S. Appl. No. 15/896,091, filed Feb. 14, 2018. [cited by applicant]