IP Library › Granted Patent US 11,508,614
Granted Patent B2
US 11,508,614 · App. 17/082,034 · Granted Nov 22, 2022

Method of forming semiconductor device having capped air gaps between buried bit lines and buried gate

Inventors: Li-Wei Feng (Kaohsiung, TW); Ying-Chiao Wang (Changhua County, TW); Tzu-Tsen Liu (Kaohsiung, TW); Tsung-Ying Tsai (Kaohsiung, TW); Chien-Ting Ho (Taichung, TW)
Assignees: UNITED MICROELECTRONICS CORP.; Fujian Jinhua Integrated Circuit Co., Ltd.
H01L21/764H01L21/0217H01L21/02164H01L27/10847H01L27/10885H01L27/249
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Quick Facts
Patent No.
US 11,508,614
App. No.
17/082,034
Granted
Nov 22, 2022
Kind
B2
Abstract

A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.

Claims (18)

1. A method of forming semiconductor memory device, comprising:

forming a plurality of bit lines extended along a first direction, and a tri-layered spacer disposed at two sides of each of the bit lines;

forming a plurality of conductive patterns extended along the first direction, the conductive patterns and the bit lines being alternately arranged along a second direction which is perpendicular to the first direction;

forming a metal layer, covering the bit lines and the conductive patterns;

removing a portion of the metal layer, to form a plurality of openings in the metal layer, the openings extended along the second direction to cross the bit lines and the conductive patterns, wherein a portion of each of the bit lines and a portion of each of the tri-layered spacers disposed at two sides of the portion of each of the bit lines are exposed from the openings;

removing a second layer of the portion of each of the tri-layered spacers exposed from the openings, to form an air-gap layer in the portion of each of the tri-layered spacers, wherein each of the air gap layers is separately disposed in the second layer along the first direction; and

after forming the air-gap layers, removing another portion of the metal layer, to form a plurality of conductive pads.

2. The method of forming a semiconductor memory device according to claim 1 , wherein the conductive pads are arranged in an array arrangement.

3. The method of forming a semiconductor memory device according to claim 1 , wherein the second layer of each of the tri-layered spacers disposed below the conductive pads is remained.

4. The method of forming a semiconductor memory device according to claim 3 , wherein the air-gap layers comprises a plurality of fragments, and the fragments of the air gap layer are separately disposed from each other and disposed along the first direction.

5. The method of forming a semiconductor memory device according to claim 4 , wherein the fragments of the air gap layer are separately disposed from each other by the remained second layer of each of the tri-layered spacers.

6. The method of forming a semiconductor memory device according to claim 1 , further comprising:

forming a capping layer on the air-gap layers before removing the another portion of the metal layer.

7. The method of forming a semiconductor memory device according to claim 6 , wherein the air-gap layers are embedded between the tri-layered spacers and the capping layer.

8. The method of forming a semiconductor memory device according to claim 1 , further comprising:

performing an etching process after forming the conductive pads, patterning the conductive patterns below the conductive pads, to form a plurality of plugs.

9. The method of forming a semiconductor memory device according to claim 1 , wherein the second layer comprises silicon oxide disposed alternately with the air gap layers in the first direction.

10. The method of forming a semiconductor memory device according to claim 1 , the second layer comprises a plurality of fragments, and the fragments of the second layer and the air gap layers are alternately arranged along the first direction.

Priority Claims (1)
CN 201710059512.9 · Jan 24, 2017 · national
Continuity (2)
Division 15873909 · Jan 18, 2018
Related Publication 20210043684A1 · Feb 11, 2021
Cited By (2)
US 12,349,340 US 12,652,797