IP Library Granted Patent US 12,349,340
Granted Patent B2
US 12,349,340 · App. 18/731,337 · Granted Jul 1, 2025

Method of forming semiconductor memory device

Inventors: Yi-Wei Chen (Taichung, TW); Hsu-Yang Wang (Tainan, TW); Chun-Chieh Chiu (Keelung, TW); Shih-Fang Tzou (Tainan, TW)
Assignees: UNITED MICROELECTRONICS CORP.; Fujian Jinhua Integrated Circuit Co., Ltd.
H10B12/485H01L21/76804H01L21/76805H01L21/76814H01L21/76819H01L21/76895H10B12/053H10B12/482
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Quick Facts
Patent No.
US 12,349,340
App. No.
18/731,337
Granted
Jul 1, 2025
Kind
B2
Abstract

A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.

Claims (20)

1. A method of forming a semiconductor memory device, comprising:

providing a substrate;

forming a semiconductor layer on the substrate;

forming a protection layer on the semiconductor layer;

forming a plug hole in the semiconductor layer;

forming a conductive primary layer on the semiconductor layer to fill in the plug hole;

performing an etching process, to partially remove the conductive primary layer to form a conductive layer in the plug hole;

forming a conductive layer in the plug hole, wherein a peripheral top surface of the conductive layer is higher than a central top surface the conductive layer;

removing the protection layer after the etching process;

wherein the peripheral top surface of the conductive layer comprises a tapered protrusion after removing the protection layer, the tapered protrusion is protruded from the semiconductor layer, without directly contacting the semiconductor layer;

oxidizing the peripheral top surface and the central top surface of the conductive layer, to form an oxide layer; and

removing the oxide layer using a wet chemical cleaning process, to form a plug in the plug hole, wherein the plug comprises a planar top surface being coplanar with a top surface of the semiconductor layer.

2. The method of forming a semiconductor memory device according 10 to claim 1 , wherein oxidizing the peripheral top surface is performed after removing the protection layer.

3. The method of forming a semiconductor memory device according to claim 1 , further comprising: oxidizing the semiconductor layer while oxidizing the conductive layer, wherein the oxide layer is also formed on the semiconductor layer.

4. The method of forming a semiconductor memory device according to claim 3 , wherein oxidizing the semiconductor layer and the conductive layer is carried out by performing an oxygen treatment process.

5. The method of forming a semiconductor memory device according to claim 4 , wherein removing the oxide layer is carried out by performing the wet chemical cleaning process using hydrofluoric acid.

6. The method of forming a semiconductor memory device according to claim 1 , further comprising:

forming a stacked structure on the top surface of the semiconductor layer and the planar top surface of the plug; and patterning the stacked structure to form a plurality of bit lines, wherein one of the bit lines directly contacts the planar top surface of the plug.

7. The method of forming a semiconductor memory device according to claim 1 , before forming the semiconductor layer, further comprising:

forming a plurality of gates in the substrate, wherein the plug is formed between two adjacent ones of the gates.

Priority Claims (1)
CN 201810425155.8 · May 7, 2018 · national
Continuity (4)
Continuation 18199346 · May 18, 2023
Division 17161685 · Jan 29, 2021
Division 16001949 · Jun 7, 2018
Related Publication 20240324187A1 · Sep 26, 2024
References Cited (32)
US 9082647B2 · Jang et al. · 2015 [cited by applicant]
US 9082755B2 · Kim · 2015 [cited by applicant]
US 9142536B2 · Kim · 2015 [cited by applicant]
US 9165934B2 · Choi et al. · 2015 [cited by applicant]
US 9178051B2 · Yu · 2015 [cited by applicant]
US 9230853B2 · Yu et al. · 2016 [cited by applicant]
US 9287395B2 · Jeong · 2016 [cited by examiner]
US 10446559B2 · Wu · 2019 [cited by applicant]
US 10475799B2 · Chen · 2019 [cited by applicant]
US 10770464B2 · Liu · 2020 [cited by applicant]
US 10818664B2 · Chang · 2020 [cited by applicant]
US 11508614B2 · Feng · 2022 [cited by applicant]
US 20100117132A1 · Chou · 2010 [cited by examiner]
US 20110086503A1 · Lim · 2011 [cited by examiner]
US 20110260288A1 · Sukekawa · 2011 [cited by examiner]
US 20120132970A1 · Park · 2012 [cited by examiner]
US 20120193796A1 · Lin et al. · 2012 [cited by applicant]
US 20120217559A1 · Kim · 2012 [cited by applicant]
US 20130264638A1 · Jang · 2013 [cited by examiner]
US 20140308794A1 · Lee · 2014 [cited by applicant]
US 20150061042A1 · Cheng · 2015 [cited by examiner]
US 20150303201A1 · Lee et al. · 2015 [cited by applicant]
US 20160072051A1 · Iwayama · 2016 [cited by examiner]
US 20160181198A1 · Kim · 2016 [cited by examiner]
US 20160247901A1 · Yuan et al. · 2016 [cited by applicant]
US 20160268262A1 · Yoo · 2016 [cited by applicant]
US 20200152649A1 · Chern · 2020 [cited by examiner]
US 20230020696A1 · Chang · 2023 [cited by examiner]
CN 102237393A · 2011 [cited by applicant]
CN 102339829A · 2012 [cited by applicant]
CN 104103577A · 2014 [cited by examiner]
Liu, the specification, including the claims, and drawings in the U.S. Appl. No. 15/896,091, filed Feb. 14, 2018. [cited by applicant]