Semiconductor memory device having capping pattern defining top surface of air gap

1. A semiconductor memory device, comprising:

a substrate including an active region;

a bit line structure extending across the active region;

a landing pad on an end portion of the active region;

a first spacer between the bit line structure and the landing pad;

a second spacer between the first spacer and the landing pad;

an air spacer between the first spacer and the second spacer;

a capping pattern between a sidewall of the landing pad and a sidewall of the bit line structure; and

a storage node contact between the landing pad and the end portion of the active region,

wherein the capping pattern is in contact with the landing pad,

wherein the capping pattern comprises the same material as the material of the landing pad that is contacted, and

wherein the capping pattern defines a top surface of the air spacer and comprises a metallic material;

wherein the active region comprises a first active region and a second active region;

a bit line node contact interposed between the bit line and the second active region;

a word line disposed in the substrate,

wherein a top surface of the word line is lower than a bottom surface of the bit line node contact;

a device isolation layer interposed between the first active region and the second active region; and

a buried pattern disposed between the storage node contact and the bit line node contact, wherein the buried pattern and an air gap overlap vertically,

wherein a top surface of the second active region is in direct contact with a bottom surface of the buried pattern and the bottom surface of the bit line node contact.

2. The semiconductor memory device of claim 1 ,

wherein the capping pattern comprises TiN or W.

3. The semiconductor memory device of claim 1 ,

wherein the capping pattern is in contact with the sidewall of the landing pad and the sidewall of the bit line structure.

4. The semiconductor memory device of claim 1 ,

wherein the capping pattern is in contact with the sidewall of the landing pad and spaced apart from the sidewall of the bit line structure.

5. The semiconductor memory device of claim 1 , further comprising:

a storage node contact between the landing pad and the end portion of the active region,

wherein the landing pad comprises:

a metal pattern; and

a barrier pattern between the metal pattern and the storage node contact, and

wherein the capping pattern is in contact with one of the metal pattern and the barrier pattern.

6. The semiconductor memory device of claim 1 ,

wherein the top surface of the air spacer is positioned higher than a top surface of the storage node contact.

7. The semiconductor memory device of claim 1 ,

wherein the capping pattern is in contact with a top surface of the first spacer and a top surface of the second spacer.

8. The semiconductor memory device of claim 1 ,

wherein the capping pattern is spaced apart from a top surface of the first spacer and a top surface of the second spacer.

9. The semiconductor memory device of claim 5 , further comprising:

a data storage member on a top surface of the landing pad; and

an upper metal pattern between the data storage member and the landing pad,

wherein the upper metal pattern comprises the same material as the landing pad and the capping pattern.

10. A semiconductor memory device, comprising:

a substrate including an active region;

a bit line structure extending across the active region, wherein the bit line structure includes a bit line and an insulating pattern stacked on each other;

a landing pad on an end portion of the active region;

a first spacer between the bit line structure and the landing pad;

a second spacer between the first spacer and the landing pad;

a gap filler layer disposed between a sidewall of the landing pad and a sidewall of the insulating pattern, wherein the gap filler layer has an upwardly-increasing width;

an air spacer between the first spacer and the second spacer; and

a capping pattern between the sidewall of the landing pad and a sidewall of the bit line structure,

wherein the capping pattern defines a top surface of the air spacer and comprises substantially the same material as the landing pad, and

wherein the gap filler layer is in direct contact with the sidewall of the insulating pattern;

wherein the active region comprises a first active region and a second active region;

a storage node contact between the landing pad and the end portion of the active region;

a bit line node contact interposed between the bit line and the second active region;

a word line disposed in the substrate,

wherein a top surface of the word line is lower than a bottom surface of the bit line node contact;

a device isolation layer interposed between the first active region and the second active region; and

a buried pattern disposed between the storage node contact and the bit line node contact, wherein the buried pattern and an air gap overlap vertically,

wherein a top surface of the second active region is in direct contact with a bottom surface of the buried pattern and the bottom surface of the bit line node contact.

11. The semiconductor memory device of claim 10 ,

wherein the capping pattern is in contact with the sidewall of the landing pad and the sidewall of the bit line structure.

12. The semiconductor memory device of claim 10 ,

wherein the capping pattern is in contact with the sidewall of the landing pad and spaced apart from the sidewall of the bit line structure.

13. The semiconductor memory device of claim 10 , further comprising:

wherein the landing pad comprises

a metal pattern; and

a barrier pattern between the metal pattern and the storage node contact, and

wherein the capping pattern comprises substantially the same material as one of the metal pattern and the barrier pattern.

14. The semiconductor memory device of claim 10 , further comprising:

wherein the top surface of the air spacer is positioned higher than a top surface of the storage node contact.

15. The semiconductor memory device of claim 10 ,

wherein the capping pattern comprises TiN or W.

16. A semiconductor memory device, comprising:

a substrate having a first active region and a second active region;

a stacked structure of a storage node contact, a landing pad and a data storage member stacked vertically on each other disposed on the first active region of the substrate;

a bit line adjacent to the stacked structure and disposed on the second active region;

a capping pattern protruding away from a sidewall of the landing pad in the stacked structure; and

an air gap disposed between a sidewall of the stacked structure and a sidewall of the bit line,

wherein an upper surface of the air gap is in contact with the capping pattern,

wherein the capping pattern comprises the same material as the material of the landing pad that is contacted;

a bit line node contact interposed between the bit line and the second active region; and

a word line disposed in the substrate,

wherein a top surface of the word line is lower than a bottom surface of the bit line node contact;

a device isolation layer interposed between the first active region and the second active region; and

a buried pattern disposed between the storage node contact and the bit line node contact, wherein the buried pattern and the air gap overlap vertically,

wherein a top surface of the second active region is in direct contact with a bottom surface of the buried pattern and the bottom surface of the bit line node contact.

17. The semiconductor memory device of claim 16 , further comprising:

a first spacer disposed between the air gap and the bit line, the first spacer being in contact with the sidewall of the bit line; and

a second spacer disposed between an upper portion of the air gap and the landing pad and between a lower portion of the air gap and the storage node contact.

18. The semiconductor memory device of claim 17 ,

wherein the air gap is defined by the first spacer, the second spacer, the capping pattern and a portion of the storage node contact, and

wherein the portion of the storage node contact is exposed between a lower end of the first spacer and a bottom portion of the second spacer.